JPS5587215A - Control data confirmation system of data processor - Google Patents

Control data confirmation system of data processor

Info

Publication number
JPS5587215A
JPS5587215A JP16407678A JP16407678A JPS5587215A JP S5587215 A JPS5587215 A JP S5587215A JP 16407678 A JP16407678 A JP 16407678A JP 16407678 A JP16407678 A JP 16407678A JP S5587215 A JPS5587215 A JP S5587215A
Authority
JP
Japan
Prior art keywords
control signal
output
data bus
cpu
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16407678A
Other languages
Japanese (ja)
Inventor
Mikio Fuse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16407678A priority Critical patent/JPS5587215A/en
Publication of JPS5587215A publication Critical patent/JPS5587215A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make sure that a control signal is being sent to an input-output device by branching the output of a latch method onto a data bus in response to an indication from CPU.
CONSTITUTION: As for assigned latch circuit LTH, a control signal is sent out via data bus DB and then stored. An output signal from latch circuit LTH is supplied to an input-output device I/O driving stage. Right after the transmission of the control signal, central controller CPU sends a command to a read bus to set flag in flag resister FR and an AND output as to BF2 and FR is sent via data bus DB, so that CPU will make sure of the control signal of the I/O driving stage by receiving the signal of DB.
COPYRIGHT: (C)1980,JPO&Japio
JP16407678A 1978-12-26 1978-12-26 Control data confirmation system of data processor Pending JPS5587215A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16407678A JPS5587215A (en) 1978-12-26 1978-12-26 Control data confirmation system of data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16407678A JPS5587215A (en) 1978-12-26 1978-12-26 Control data confirmation system of data processor

Publications (1)

Publication Number Publication Date
JPS5587215A true JPS5587215A (en) 1980-07-01

Family

ID=15786314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16407678A Pending JPS5587215A (en) 1978-12-26 1978-12-26 Control data confirmation system of data processor

Country Status (1)

Country Link
JP (1) JPS5587215A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476246A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd System for testing common bus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144839A (en) * 1974-10-16 1976-04-16 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144839A (en) * 1974-10-16 1976-04-16 Hitachi Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476246A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd System for testing common bus

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