JPS5582462A - Both polarity charge input unit - Google Patents

Both polarity charge input unit

Info

Publication number
JPS5582462A
JPS5582462A JP15558178A JP15558178A JPS5582462A JP S5582462 A JPS5582462 A JP S5582462A JP 15558178 A JP15558178 A JP 15558178A JP 15558178 A JP15558178 A JP 15558178A JP S5582462 A JPS5582462 A JP S5582462A
Authority
JP
Japan
Prior art keywords
positive
gate
charge
negative
input unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15558178A
Other languages
Japanese (ja)
Other versions
JPS5726428B2 (en
Inventor
Yoshihiro Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15558178A priority Critical patent/JPS5582462A/en
Publication of JPS5582462A publication Critical patent/JPS5582462A/en
Publication of JPS5726428B2 publication Critical patent/JPS5726428B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76808—Input structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To decrease the errors of the quantities of both positive and negative charge for providing with weight coefficients by mounting the first charge input unit with positive polarity in double or triple gate structure and the second carge input unit with negative polarity in triple gate structure to an input coefficient type charge transmission device. CONSTITUTION:Both positive and negative input units applies signal voltage Vs to the first gate G1 with larger insulating film thickness, and charge in a well is measured by means of a well just under the second gate G2 with smaller insulating film thickness. Thus, the control characteristics of charge measured by bias voltage VG2 and the control characteristics of the height of a potential barrier layer by the signals Vs stacking to the bias voltage completely become to the same between the both positive and negative input units, and the quantities of both positive and negative charge are introduced into a CCD transmission passage highly accurate without unevenness. In the negative coefficient input unit, relative positions between the first gate G1 and the second gate G2 are made inverse to the positive coefficient input unit, and the third gate G3 for applying transmission pulses phi1 is mounted.
JP15558178A 1978-12-15 1978-12-15 Both polarity charge input unit Granted JPS5582462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15558178A JPS5582462A (en) 1978-12-15 1978-12-15 Both polarity charge input unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15558178A JPS5582462A (en) 1978-12-15 1978-12-15 Both polarity charge input unit

Publications (2)

Publication Number Publication Date
JPS5582462A true JPS5582462A (en) 1980-06-21
JPS5726428B2 JPS5726428B2 (en) 1982-06-04

Family

ID=15609164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15558178A Granted JPS5582462A (en) 1978-12-15 1978-12-15 Both polarity charge input unit

Country Status (1)

Country Link
JP (1) JPS5582462A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453783A (en) * 1992-09-02 1995-09-26 Martin Marietta Corporation General absolute value circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0366848A (en) * 1989-08-02 1991-03-22 Kozaburo Mizutani Side gutter for watercourse and concrete-plated watercourse

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453783A (en) * 1992-09-02 1995-09-26 Martin Marietta Corporation General absolute value circuit

Also Published As

Publication number Publication date
JPS5726428B2 (en) 1982-06-04

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