JPS5582366A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS5582366A
JPS5582366A JP15803678A JP15803678A JPS5582366A JP S5582366 A JPS5582366 A JP S5582366A JP 15803678 A JP15803678 A JP 15803678A JP 15803678 A JP15803678 A JP 15803678A JP S5582366 A JPS5582366 A JP S5582366A
Authority
JP
Japan
Prior art keywords
level
memory unit
shared memory
clock
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15803678A
Other languages
Japanese (ja)
Other versions
JPS589461B2 (en
Inventor
Tsutomu Yanagisawa
Mikio Fuse
Harumitsu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53158036A priority Critical patent/JPS589461B2/en
Publication of JPS5582366A publication Critical patent/JPS5582366A/en
Publication of JPS589461B2 publication Critical patent/JPS589461B2/en
Expired legal-status Critical Current

Links

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  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To make it possible to access a shared memory unit without any mutual influence of processors by providing two processors using non-duplicate two-phase clocks and the shared memory unit shared by them.
CONSTITUTION: Clocks ϕ1 and ϕ2 of master-side microprocessor 2 are shifted in phase from clocks ϕ1 and ϕ2 of slave-side microprocessor 3 by 180° respectively. DMAC control signal G is high-level for high-level clock ϕ2 of processor 2 and is fixed-level for low-level clock ϕ2 of processor 2. That is, processor 2 is connected to shared memory unit 7 when clock ϕ2 of the master-side microprocessor is high-level, and processsor 3 is connected to shared memory unit 7 when clock ϕ2 of the slave- side microprocessor is high-level. In case of read access of processors 2 and 3, they are not affected by each other because busses between them and shared memory unit 7 are disconnected.
COPYRIGHT: (C)1980,JPO&Japio
JP53158036A 1978-12-18 1978-12-18 multiprocessor system Expired JPS589461B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53158036A JPS589461B2 (en) 1978-12-18 1978-12-18 multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53158036A JPS589461B2 (en) 1978-12-18 1978-12-18 multiprocessor system

Publications (2)

Publication Number Publication Date
JPS5582366A true JPS5582366A (en) 1980-06-21
JPS589461B2 JPS589461B2 (en) 1983-02-21

Family

ID=15662864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53158036A Expired JPS589461B2 (en) 1978-12-18 1978-12-18 multiprocessor system

Country Status (1)

Country Link
JP (1) JPS589461B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59292A (en) * 1982-06-23 1984-01-05 Fujitsu Ltd Memory access system for subscriber's circuit information
JPS5962966A (en) * 1982-09-30 1984-04-10 Shin Meiwa Ind Co Ltd Data transfer circuit between cpus
JPS59198045A (en) * 1983-04-25 1984-11-09 Toyota Motor Corp Multiplex transmitter of signal
JPS61177564A (en) * 1985-02-01 1986-08-09 Neoroogu Denshi Kk Shared storage device
JPS61184658A (en) * 1985-02-12 1986-08-18 Fujitsu Ten Ltd Distribution control system
JPS61237150A (en) * 1985-04-15 1986-10-22 Hitachi Ltd Arithmetic system for input/output processing
JPS633359A (en) * 1986-06-20 1988-01-08 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Digital information processing system
JPS6376048A (en) * 1986-09-19 1988-04-06 Fujitsu Ltd Input/output control device
WO1996001451A1 (en) * 1994-07-04 1996-01-18 Creative Design Inc. Coprocessor system and auxiliary arithmetic function-carrying external memory
CN103412848A (en) * 2013-05-11 2013-11-27 中国科学技术大学 Method for sharing single program memory by four-core processor system

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59292A (en) * 1982-06-23 1984-01-05 Fujitsu Ltd Memory access system for subscriber's circuit information
JPS5962966A (en) * 1982-09-30 1984-04-10 Shin Meiwa Ind Co Ltd Data transfer circuit between cpus
JPS59198045A (en) * 1983-04-25 1984-11-09 Toyota Motor Corp Multiplex transmitter of signal
JPS61177564A (en) * 1985-02-01 1986-08-09 Neoroogu Denshi Kk Shared storage device
JPS61184658A (en) * 1985-02-12 1986-08-18 Fujitsu Ten Ltd Distribution control system
JPH051504B2 (en) * 1985-04-15 1993-01-08 Hitachi Ltd
JPS61237150A (en) * 1985-04-15 1986-10-22 Hitachi Ltd Arithmetic system for input/output processing
JPS633359A (en) * 1986-06-20 1988-01-08 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Digital information processing system
JPH056906B2 (en) * 1986-06-20 1993-01-27 Intaanashonaru Bijinesu Mashiinzu Corp
JPS6376048A (en) * 1986-09-19 1988-04-06 Fujitsu Ltd Input/output control device
WO1996001451A1 (en) * 1994-07-04 1996-01-18 Creative Design Inc. Coprocessor system and auxiliary arithmetic function-carrying external memory
CN1097784C (en) * 1994-07-04 2003-01-01 任天堂株式会社 Coorperating processing system and outer memory means with assisting calculating function
CN103412848A (en) * 2013-05-11 2013-11-27 中国科学技术大学 Method for sharing single program memory by four-core processor system
CN103412848B (en) * 2013-05-11 2016-05-25 中国科学技术大学 A kind of four core processor systems are shared the method for single program storage

Also Published As

Publication number Publication date
JPS589461B2 (en) 1983-02-21

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