JPS5580888A - Read only memory circuit - Google Patents

Read only memory circuit

Info

Publication number
JPS5580888A
JPS5580888A JP15442978A JP15442978A JPS5580888A JP S5580888 A JPS5580888 A JP S5580888A JP 15442978 A JP15442978 A JP 15442978A JP 15442978 A JP15442978 A JP 15442978A JP S5580888 A JPS5580888 A JP S5580888A
Authority
JP
Japan
Prior art keywords
comparator
value information
circuit
comparison output
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15442978A
Other languages
Japanese (ja)
Inventor
Nobuaki Ieda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15442978A priority Critical patent/JPS5580888A/en
Publication of JPS5580888A publication Critical patent/JPS5580888A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Abstract

PURPOSE:To realize the reading of the multi-value information through a simple and small-size constitution by giving a comparison between several sets of different reference signals corresponding to the multi-value information and the signals read for the logic process. CONSTITUTION:The discharge time constant varies according to the conductance of transistor Qij of memory circuit Mij forming ROM, and thus the curve of the voltage changes to the time. Reference voltage V1-V3 corresponding to these curves are applied to comparators A3-A1 from reference voltage generator circuit R of identifier circuit Y. Then the quadruple information such as [11], [10], [01] and [00] are identified via amplifiers AM1 and AM2 and by the comparison output of comparator A1 passing through OR gate OR to which the comparison output of comparator A2 as well as the comparison output of comparator A3 are applied through AND gate AN which is controlled by inhibit circuit IN. In such way, the multi-value information can be identified for reading through a simple and small- size constitution and with omission of a number of cells.
JP15442978A 1978-12-12 1978-12-12 Read only memory circuit Pending JPS5580888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15442978A JPS5580888A (en) 1978-12-12 1978-12-12 Read only memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15442978A JPS5580888A (en) 1978-12-12 1978-12-12 Read only memory circuit

Publications (1)

Publication Number Publication Date
JPS5580888A true JPS5580888A (en) 1980-06-18

Family

ID=15583976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15442978A Pending JPS5580888A (en) 1978-12-12 1978-12-12 Read only memory circuit

Country Status (1)

Country Link
JP (1) JPS5580888A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0072845A1 (en) * 1981-02-25 1983-03-02 Motorola Inc Memory system having memory cells capable of storing more than two states.
EP0078439A2 (en) * 1981-11-03 1983-05-11 International Business Machines Corporation Read only storage using a four state cell
JPS58137181A (en) * 1982-02-05 1983-08-15 Toshiba Corp Semiconductor memory
US5526306A (en) * 1994-02-10 1996-06-11 Mega Chips Corporation Semiconductor memory device and method of fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5381024A (en) * 1976-12-27 1978-07-18 Fujitsu Ltd Semiconductor memory divice
JPS54162934A (en) * 1978-06-13 1979-12-25 Ibm Read only memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5381024A (en) * 1976-12-27 1978-07-18 Fujitsu Ltd Semiconductor memory divice
JPS54162934A (en) * 1978-06-13 1979-12-25 Ibm Read only memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0072845A1 (en) * 1981-02-25 1983-03-02 Motorola Inc Memory system having memory cells capable of storing more than two states.
EP0078439A2 (en) * 1981-11-03 1983-05-11 International Business Machines Corporation Read only storage using a four state cell
JPS58137181A (en) * 1982-02-05 1983-08-15 Toshiba Corp Semiconductor memory
JPH0318275B2 (en) * 1982-02-05 1991-03-12 Tokyo Shibaura Electric Co
US5526306A (en) * 1994-02-10 1996-06-11 Mega Chips Corporation Semiconductor memory device and method of fabricating the same

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