JPS54161853A - Read-only memory - Google Patents

Read-only memory

Info

Publication number
JPS54161853A
JPS54161853A JP7057478A JP7057478A JPS54161853A JP S54161853 A JPS54161853 A JP S54161853A JP 7057478 A JP7057478 A JP 7057478A JP 7057478 A JP7057478 A JP 7057478A JP S54161853 A JPS54161853 A JP S54161853A
Authority
JP
Japan
Prior art keywords
cell
memory
transistor
levels
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7057478A
Other languages
Japanese (ja)
Inventor
Shinji Morozumi
Tatsuji Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP7057478A priority Critical patent/JPS54161853A/en
Publication of JPS54161853A publication Critical patent/JPS54161853A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To obtain a large-capacity memory suited for the IC formation by forming the transistor at each memory cell and then using properly the threshold levels of the transistors of more than two levels. CONSTITUTION:The transistor is formed to each of cells 21-28 of ROM. And the threshold levels of cell 22, 26 and 28 are set to, for example, 2V at the first formation time. Then the ion implantation of boron is applied to cell 21 and 24 to secure reduction by 0.5V, and furthermore cell 25 and 27 are set to 1.5V and with cell 23 set to 0.5V each. Thus, four levels are secured. As a result, the 4-state program is possible with one transistor, thus increasing the memory capacity for each of cells 21-28.
JP7057478A 1978-06-12 1978-06-12 Read-only memory Pending JPS54161853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7057478A JPS54161853A (en) 1978-06-12 1978-06-12 Read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7057478A JPS54161853A (en) 1978-06-12 1978-06-12 Read-only memory

Publications (1)

Publication Number Publication Date
JPS54161853A true JPS54161853A (en) 1979-12-21

Family

ID=13435449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7057478A Pending JPS54161853A (en) 1978-06-12 1978-06-12 Read-only memory

Country Status (1)

Country Link
JP (1) JPS54161853A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1982002977A1 (en) * 1981-02-25 1982-09-02 Inc Motorola Memory cell having more than two voltage levels
JPS57143797A (en) * 1981-01-28 1982-09-06 Gen Instrument Corp Read only memory
JPS58500147A (en) * 1981-02-25 1983-01-20 モトロ−ラ・インコ−ポレ−テツド A memory device having memory cells that can store two or more states
US4388702A (en) * 1981-08-21 1983-06-14 Mostek Corporation Multi-bit read only memory circuit
JPS59121696A (en) * 1982-12-28 1984-07-13 Toshiba Corp Non-volatile semiconductor memory
US5512504A (en) * 1992-12-21 1996-04-30 National Semiconductor Corporation Method of making a memory array with field oxide islands eliminated

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143797A (en) * 1981-01-28 1982-09-06 Gen Instrument Corp Read only memory
US4404655A (en) * 1981-01-28 1983-09-13 General Instrument Corporation Data sense apparatus for use in multi-threshold read only memory
JPH0154800B2 (en) * 1981-01-28 1989-11-21 Gen Instrument Corp
WO1982002977A1 (en) * 1981-02-25 1982-09-02 Inc Motorola Memory cell having more than two voltage levels
JPS58500147A (en) * 1981-02-25 1983-01-20 モトロ−ラ・インコ−ポレ−テツド A memory device having memory cells that can store two or more states
US4388702A (en) * 1981-08-21 1983-06-14 Mostek Corporation Multi-bit read only memory circuit
JPS59121696A (en) * 1982-12-28 1984-07-13 Toshiba Corp Non-volatile semiconductor memory
JPH0547920B2 (en) * 1982-12-28 1993-07-20 Tokyo Shibaura Electric Co
US5512504A (en) * 1992-12-21 1996-04-30 National Semiconductor Corporation Method of making a memory array with field oxide islands eliminated

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