JPH0547920B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a nonvolatile memory cell having data for a plurality of bits in one memory cell. [Technical background of the invention and its problems] Conventionally, semiconductor memory, especially ROM (Read Only
For example, a method has been proposed for storing 2 bits of data in one cell by differentiating the threshold voltage of the memory cell into four types. There is an advantage that the area occupied by the cell can be halved by storing data for 20 minutes. The data for 2 bits is “0”, “0”; “1”, “0”; “0”, “1”;
“1”,
There are four combinations of "1", and this is made to correspond to its threshold voltage, and one of the four data is distinguished depending on the potential of the data line when that memory cell is selected, and 2 bits of data are The data is read out. However, conventionally, the threshold voltage of a memory cell has been controlled by changing the gate voltage or drain voltage. Therefore, with this method, it is difficult to control the threshold voltage due to variations in cell gate length and oxide film thickness, and even if writing is performed under the same voltage conditions, the threshold voltage are not the same but vary, which causes a decrease in yield. [Object of the invention] The present invention has been made in view of the above circumstances, and has the following features:
An object of the present invention is to provide a nonvolatile semiconductor memory which weights the threshold values of one memory cell and stores data of a plurality of bits, in which the threshold values of the memory cells can be easily controlled. [Summary of the Invention] In order to achieve the above object, the present invention sets input data according to the magnitude of the threshold voltage to be set for one memory cell, and sets input data according to the magnitude of the threshold voltage to be set for one memory cell. The bit output is fed back to change the threshold value of the memory cell until a plurality of output bits and a plurality of input data bits match each other. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 is write input data
An AND circuit to which Din0 and Din1 are supplied; 2 is a NOR circuit that controls transistor 3 and supplies high voltage Vp (approximately 20 V) to point a; 4 is a flip-flop; 5
is an inverter, 6 is a NAND circuit, 7 and 8 are comparators that compare the input data and output data, which will be described later.
9 is a column selection transistor; 10 is a memory cell in which electrons are injected by writing and the threshold voltage changes; 11 and 12 are transistors that lower the drain voltage of the memory cell 10 to prevent erroneous writing when reading data; Load transistors, 14 to 16 are reference voltages C ₁ to _{C 3} (C ₁ > C ₂ > C ₃ )
and a sense amplifier which inputs the voltage at point A via the transistor 12, and 17 is the sense amplifier output D ₁ ~
Output Dout0 created based on D ₂ as input,
This is a conversion circuit that derives Dout1, and the output Dout0 and
Dout1 is fed back to comparators 7 and 8. The part 18 surrounded by the dashed-dotted line in Fig. 1
By comparing the potential at point b, which changes depending on the threshold voltage of the memory cell, with three reference voltage levels, C ₁ , C ₂ , and C ₃ , the 2-bit data as shown in Table 1 below is obtained. This is a circuit that outputs one of four combinations of outputs Dout0 and Dout1.

〔Effect of the invention〕

As explained above, according to the present invention, in a nonvolatile memory that weights the threshold value of one memory cell and stores data for multiple bits to reduce the area occupied by the memory cell, write signals and read signals can be A nonvolatile semiconductor memory with improved yield can be provided because the amount of data written to memory cells can be sequentially read and monitored using signals, and one of multiple threshold values can be set with good controllability. It is.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the same configuration. 1, 6...AND circuit, 2...NOR circuit, 3,
9-13...Transistor, 4...Flip-flop, 6...NAND circuit, 7, 8...Comparator, 1
4 to 16...Sense amplifier, 17...Conversion circuit.

Claims (1)

[Scope of Claims] 1. A nonvolatile semiconductor memory cell, means for writing data into the memory cell, means for reading data stored in the memory cell, and a means for reading data stored in the memory cell; a plurality of sense amplifiers that are used for both data writing and data reading, detecting the voltage at the connection point between the memory cell and the load element caused by the output data, and comparing it with each reference voltage level to obtain a logical output;
Based on the logic output of this sense amplifier, there is a conversion circuit that sends out a logic output corresponding to the threshold voltage of the memory cell at that time, and the output of this conversion circuit is the input data to be set for multiple types. A nonvolatile semiconductor memory comprising: a logic circuit that repeats writing of the data and reading of the data until the data corresponds to the corresponding one. 2. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory cell has a threshold voltage determined according to injection of electrons.