US5867427A - Electrically writable nonvolatile semiconductor memory device - Google Patents
Electrically writable nonvolatile semiconductor memory device Download PDFInfo
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- US5867427A US5867427A US08/908,673 US90867397A US5867427A US 5867427 A US5867427 A US 5867427A US 90867397 A US90867397 A US 90867397A US 5867427 A US5867427 A US 5867427A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5624—Concurrent multilevel programming and programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
Definitions
- the present invention relates to an electrically writable nonvolatile semiconductor memory device, particularly one capable of setting the threshold potential of a cell transistor assigned to a writing operation rapidly and accurately.
- a flash memory is attracting increasing attention as a memory for allowing data to be rewritten and for holding data even at the time of power down.
- a channel hot electron injection scheme or a Fowler-Nodeheim tunneling scheme is often used. These two schemes both set the threshold voltage of a cell transistor corresponding to a write address at a preselected potential, and determine data to be read on the basis of a current to flow through the transistor and derived from the above potential.
- An electrically writable nonvolatile semiconductor memory device including a memory cell transistor of the present invention has a current feeding circuit for feeding a write current to the memory cell transistor during writing, a write current sensing circuit for producing a sense signal when the write current reaches a preselected value, and a stopping circuit for stopping a writing operation in response to the sense signal.
- FIG. 1 is a block diagram schematically showing a conventional nonvolatile semiconductor memory device
- FIG. 2 is a flowchart demonstrating a specific writing routine particular to the embodiment shown in FIG. 1;
- FIG. 3 is a graph showing a relation between a writing time and a threshold voltage assigned to a cell transistor
- FIG. 4 shows a period of time necessary for the conventional memory device to complete a writing operation
- FIG. 5 is a graph showing a threshold value distribution of a cell transistor included in a multivalue nonvolatile semiconductor memory device
- FIG. 6 is a circuit diagram showing a multilevel electrically writable nonvolatile semiconductor memory device embodying the present invention
- FIG. 7 is a timing chart showing the variation of potentials appearing at various points shown in FIG. 6;
- FIG. 8 is a circuit diagram showing an alternative embodiment of the present invention.
- FIG. 9 is a graph showing the variations of potentials appearing at various points shown in FIG. 8.
- FIG. 10 compares the writing time of the conventional memory device and the writing time achievable with the embodiment shown in FIG. 8.
- FIG. 1 shows specific circuitry representative of a conventional nonvolatile semiconductor memory device using the channel hot electron injection scheme.
- the circuitry is made up of a first power source circuit (power source 1) 62, a second power source circuit (power source 2) 63, a sense amplifier 64, a reference current source 65, a sequencer 66, a driver 69, a select transistor (n-channel MOS (Metal Oxide Semiconductor) transistor) 70, an n-channel MOS transistor 71, and a write controller 72.
- the first power source 62 feeds a write potential to the drain of a cell transistor 61 at the time of writing.
- the second power source 63 sets a particular potential of a word line in accordance with a mode.
- the sense amplifier 64 senses a current flowing through the cell transistor 61 and outputs data corresponding to the threshold potential of the transistor 61.
- the reference power source 65 sets a reference current source for the sense amplifier 64.
- the driver 69 has a p-channel MOS transistor 67 and an n-channel MOS transistor 68 and feeds a write potential to the gate of the cell transistor 61 at the time of writing or feeds a read potential to the same at the same time of reading.
- the select transistor 70 feeds a write potential to the drain of the cell transistor 61 at the same time of writing or feeds a read potential to the same at the time of reading.
- the n-channel MOS transistor 71 plays the role of a switching device for determining whether or not to feed the write potential to the cell transistor 61.
- the write controller 72 controls the operation of the transistor 71.
- FIG. 2 demonstrates the operation of the circuitry shown in FIG. 1.
- a major part of the operation to be described is taught in Japanese Patent Publication No. 1-42080 as prior art. Briefly, data is written to a cell transistor selected by varying the threshold potential of the transistor. After the writing of the data, whether or not the cell transistor has reached its threshold potential is determined. If the answer of this decision is negative, the same data is again written to the cell transistor, and then the above decision is repeated. Such a procedure is repeated a preselected number of times. The writing operation fails when the preselected number of times is reached.
- step S1 data to be written is input (step S1). Then, the number of times of writing to be repeated (retry counter) I is reset (step S2). Thereafter, data is written to a cell selected (step S3).
- the potential output from the second power source 63 is selectively fed to a word line 73, FIG. 1, from the second power source circuit 63 as a write potential (e.g. 12V).
- the write potential e.g. 6 V
- electrons are injected into the floating gate of the cell transistor 61 by hot electron injection, raising the threshold voltage of the transistor 61.
- step S4 determines whether or not the voltage of the cell transistor 61 has reached its preselected voltage.
- the potential to be output from the second power source 63 is set at a write confirmation potential (e.g. 7 V) and applied to the cell transistor 61.
- the transistor 71 is turned off.
- the sense amplifier 64 is rendered active in order to apply the read potential to the drain of the cell transistor 61 and effect a reading operation.
- the writing operation causes the threshold voltage of the cell transistor to rise. Therefore, whether or not the cell transistor has reached the threshold voltage is determined on the basis of whether or not a current is flowing through the cell transistor 61 with the write confirmation potential being applied to the gate of the cell transistor.
- step S5 If the answer of the step S4 is positive (YES), the writing operation is stopped (step S5). If the answer of the step S4 is negative (NO), whether or not the retry counter I has reached the preselected number of times, i.e., the upper limit (step S6) is determined. If the answer of the step S6 is NO, the retry counter I is incremented by 1 (one) in order to retry the writing operation (step S7). If the answer of the step S6 is YES, the writing operation is determined to have failed and is stopped. The above procedure is executed by the sequencer 66.
- FIG. 3 shows a relation between the writing time and the threshold voltage of the cell transistor.
- FIG. 4 shows a relation between the total writing time and the writing operation and write confirming operation.
- the Fowler-Nodeheim tunneling scheme is identical with the channel hot electron injection scheme except that a potential for causing Fowler-Nodeheim tunneling to occur is applied to each contact of the cell transistor.
- data is written to a multivalue semiconductor memory device in basically the same manner that it is written to a flash memory. The difference is that the multivalue semiconductor memory must have its threshold voltage set with accuracy, and therefore must repeat the write confirming operation more frequently than the flash memory.
- FIG. 5 shows a threshold potential distribution particular to a multivalue nonvolatile semiconductor memory device.
- the threshold potential of this type of memory device is also raised during writing. A writing operation exceeding a preselected threshold potential would result in erroneous writing. Therefore, it is a common practice to repeat the writing operation and write confirming operation little by little, thereby adjusting the threshold of a cell transistor.
- any one of the conventional electrically writable nonvolatile semiconductor memory devices it is difficult to minimize the substantial period of time necessary for the writing operation to be completed, and to set a desired threshold with accuracy. Specifically, the writing operation must be followed by the write confirming operation; the writing operation and write confirming operation must be repeated a number of times satisfying the desired accuracy of the threshold (see FIG. 4). This increases the substantial period of time for the writing operation to be completed. Should the number of times of write confirming operation be reduced in order to reduce the substantial writing time, the deviation from the desired threshold would increase to a critical degree.
- the memory device includes a memory cell transistor 111.
- N-channel MOS transistors 113 and 114 are connected between the memory cell transistor 111 and a first power source terminal 112.
- a latch circuit 118 has NAND gates 115, 116 and 117 connected together, as illustrated.
- a level shifter 125 is connected to a second power source terminal 119 and made up of p-channel MOS transistors 127 and an n-channel MOS transistors 122 and 123, and an inverter 124.
- a driver 129 is connected to a third power source terminal 126 and made up of a p-channel MOS transistor 127 and an n-channel MOS transistor 128.
- a differential amplifier circuit 139 is implemented by p-channel MOS transistors 130 and 131, n-channel MOS transistors 132, 133 and 134, a first, a second and a third reference current source 135, 136 and 137 (REF 1 through REF 3), a reference current source selector 138, and the transistor 114.
- Another differential amplifier circuit 144 has p-channel MOS transistors 140 and 141 and n-channel MOS transistors 142 and 143.
- the latch circuit 118 is reset when a low (L) level preset signal (PST) is input thereto. While the latch circuit 118 is in its reset state, the level shifter 125 shifts the level of a potential applied to the power source terminal 119 and thereby sets at a point A a potential necessary for clamping the drain potential of the cell transistor 111. At this instant, when a high (H) level is input to the transistor 114 as a write control signal ACT, the write potential applied to the power source terminal 112 is fed to the drain of the cell transistor 111.
- L low
- PST level preset signal
- the latch circuit 118 is set when a write current meant for the cell transistor 111 falls below a preselected value, as will be described specifically later. In this case, the level of the potential at the point A goes L, so that the writing operation is stopped even if the write control signal ACT is in its H level.
- the driver 129 To write data in the cell transistor 111, it is necessary for the driver 129 to feed a preselected potential to a word line W in response to a word line select signal BW. That is, if such a potential is applied to the word line W and if the above write potential is applied to the drain of the cell transistor 111, data is written to the cell transistor 111 by hot electron injection.
- the differential amplifier circuit 139 senses a change in a current I 11 flowing through the cell transistor 111, and varies a potential at a point B accordingly.
- the first to third reference current sources 135-137 each outputs a particular current.
- the output currents of the reference current sources 135-137 respectively correspond to desired threshold values to be set in the cell transistor.
- One of the output currents of the reference current sources 135-137 selected by the reference current source selector 138 is compared to the current I 11 (actually I 12 ) that is decreasing due to the writing operation. When the current I 11 reaches a preselected value, the potential at the point B is caused to go L.
- the other differential amplifier circuit 144 amplifies the fine amplitude of the potential at the point B in response to a signal VR. In a word, this circuit 144 fixes a potential at a point C at the H level in response to the change of the point B to the L level. If desired, the circuit 144 may be replaced with, e.g., an inverter so long as it can satisfy the preselected condition.
- the latch circuit 118 When the potential at the point C is fixed at the H level by the differential amplifier circuit 144, the latch circuit 118 is set and causes the level shifter 125 to change the level at the point B to L. Consequently, the potential at the power source terminal 112 is not fed to the drain of the cell transistor 111, causing the writing operation to be stopped without regard to the potential of the write control signal ACT.
- the embodiment controls the writing operation on the basis of the threshold value of the cell transistor which varies due to the writing operation and, in turn, causes the current flowing through the cell transistor to vary. That is, while executing the writing operation, the embodiment measures a current flowing through the cell transistor and determines whether or not to continue the writing operation, depending on whether or not the above current reaches a preselected value. This eliminates the need for the conventional write confirming operation independent of the writing operation and thereby optimizes (reduces) the substantial period of time used from the beginning to the end of the writing operation.
- FIG. 7 demonstrate how the potentials at the various portions shown in FIG. 6 vary specifically.
- a desired threshold voltage matching with data to be written is set because the embodiment implements multivalue electrical writing.
- one of the three reference current sources 135-137 is selected and used to determine whether or not to end the writing operation.
- the write control signal ACT and preset signal PST each is held in its L level or preset state.
- a write set potential is fed from the power source terminal 119 to the point A via the level shifter 125.
- the word select signal BW is brought to its L level in order to apply a write potential (e.g. 12 V) to the word line W.
- This is the preparatory stage in which the memory device is ready to write data in response to a change of the write control data ACT from the L level to the H level.
- the threshold value of the cell transistor 111 sequentially increases as the writing operation proceeds.
- the rise of the threshold voltage causes the write current I 11 to fall. Consequently, the potential at the point B falls on the basis of the comparison between the write current I 11 and the reference current. Therefore, the transistor 142 turns off and causes the potential at point C to go H.
- the latch circuit 118 is set and causes the level shifter 125 to change the potential at the point A to the L level. This turns off the transistor 113 and thereby ends the writing operation.
- an optimal threshold value for the cell transistor 111 can be set only by the writing operation, i.e., without resorting to an exclusive write confirmation sequence. This realizes both the optimal writing time and the accurate setting of a threshold potential.
- FIGS. 8 and 9 show an alternative embodiment of the present invention.
- This embodiment pertains to a multivalue electrically writable nonvolatile semiconductor memory device implemented by the Fowler-Nodeheim tunneling scheme.
- FIG. 8 the same structural elements as the elements shown in FIG. 1 are designated by like reference numerals, and a detailed description thereof will not be made in order to avoid redundancy.
- the latch circuit 118 is reset by the L level preset signal PST, as in the previous embodiment, and fixes a potential at a point D at the H level.
- the latch circuit 118 is set by the H level signal input from the differential amplifier circuit 142.
- the transistor 144 turns on in response to the write control signal ACT of H level.
- a read potential which would not obstruct writing based on Fowler-Nodeheim tunneling is applied from the power source terminal 112 to the drain of the cell transistor 111.
- a word decoder 317 applies a write potential from a power source terminal 318 to the word line W in response to a second write control signal XACT and word line select signals (A0 and A1).
- the word decoder 317 causes the word line W to go L without regard to the level of the second write control signal XACT.
- the differential amplifier 139 causes the potential at the point E to vary in accordance with a write current I 31 flowing through the cell transistor 111, as in the previous embodiment.
- the variation of the potential at the point E depends on the current values assigned to the reference current sources 135-137 beforehand. Specifically, when the write current I 31 reaches a preselected value based on the comparison between the current value of the reference current source selected by the selector 138 and the write current I 31 (current I 32 ), a point F is caused to go L.
- the differential amplifier circuit 144 causes the potential at the point F to vary in accordance with the potential at the point E. Specifically, when the point E goes L, the circuit 144 fixes the point F at the H level and thereby sets the latch circuit 118.
- the circuit 144 may, of course, be implemented by an inverter, as in the previous embodiment.
- the latch circuit 118 is set and changes its output to the L level. As a result, the potential on the word line W goes L and stops the writing operation.
- a reference current source matching with a desired threshold voltage is selected on the basis of data to be written, as in the previous embodiment.
- the first and second write control signals ACT and XACT and preset signal PST each is brought to the L level or preset state.
- the word line select signals A0 and A1 are caused to go H, and then the second write control signal XACT is caused to go H.
- a write potential e.g. 18 V
- the first write control signal ACT is caused to go H in order to start a writing operation.
- the preset signal PST is caused to go H in order to render the latch circuit 118 active.
- the threshold voltage of the cell transistor 111 sequentially rises, causing the write current I 31 to sequentially fall.
- the potential at the point E which is the result of comparison between the write current I 31 and the reference current, falls and turns off the transistor 142. Consequently, the point F goes H and sets the latch circuit 118.
- the output of the word decoder 317 goes low and stops the writing operation.
- FIG. 10 shows a difference between the writing time of the conventional memory device and the writing time achievable with the illustrative embodiment.
- both the optimal writing time and the accurate setting of a threshold voltage are attainable by effecting only the writing operation, i.e., without resorting to a write confirmation sequence.
- the present invention provides an electrically writable nonvolatile semiconductor memory device eliminating the need for a write confirming operation. This is because the memory device detects a write current flowing through a memory cell transistor during writing and stops writing when the write current reaches a preselected value. Further, a threshold value for the memory cell transistor can be accurately set only if a relation between a threshold voltage and the write current is determined with accuracy beforehand. The memory device therefore realizes both the accurate writing to a desired threshold voltage and the noticeable decrease in writing time, which are particularly desirable with a multivalue semiconductor memory device.
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Abstract
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Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP8-208583 | 1996-08-07 | ||
JP20858396A JPH1055690A (en) | 1996-08-07 | 1996-08-07 | Electrically writable non-volatile semiconductor memory |
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US5867427A true US5867427A (en) | 1999-02-02 |
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US08/908,673 Expired - Lifetime US5867427A (en) | 1996-08-07 | 1997-08-07 | Electrically writable nonvolatile semiconductor memory device |
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KR (1) | KR19980018610A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6094374A (en) * | 1998-03-25 | 2000-07-25 | Nec Corporation | Nonvolatile semiconductor memory device including sense amplifier having verification circuit |
US6185130B1 (en) * | 1999-10-18 | 2001-02-06 | Advanced Micro Devices, Inc. | Programmable current source |
EP1074995A1 (en) * | 1999-08-03 | 2001-02-07 | STMicroelectronics S.r.l. | Method for programming multi-level non-volatile memories by controlling the gate voltage |
EP1079394A4 (en) * | 1998-04-17 | 2001-07-11 | Ultraclean Technology Res Inst | Semiconductor memory |
US6498757B2 (en) * | 2000-11-23 | 2002-12-24 | Macronix International Co., Ltd. | Structure to inspect high/low of memory cell threshold voltage using current mode sense amplifier |
US20040114444A1 (en) * | 2002-12-04 | 2004-06-17 | Sharp Kabushiki Kaisha | Semiconductor memory device and method for programming and erasing a memory cell |
US20060291285A1 (en) * | 2003-02-06 | 2006-12-28 | Nima Mokhlesi | System and method for programming cells in non-volatile integrated memory devices |
US20070206425A1 (en) * | 2006-03-02 | 2007-09-06 | Fujitsu Limited | Semiconductor memory device |
US20080123427A1 (en) * | 2006-11-28 | 2008-05-29 | Macronix International Co., Ltd. | Flash memory, program circuit and program method thereof |
US20110063908A1 (en) * | 2001-04-27 | 2011-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile Memory, Verify Method Therefor, and Semiconductor Device Using the Nonvolatile Memory |
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Publication number | Priority date | Publication date | Assignee | Title |
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US7729165B2 (en) * | 2007-03-29 | 2010-06-01 | Flashsilicon, Incorporation | Self-adaptive and self-calibrated multiple-level non-volatile memories |
JP4901827B2 (en) * | 2008-08-22 | 2012-03-21 | ペグレ・セミコンダクターズ・リミテッド・ライアビリティ・カンパニー | Semiconductor storage device, writing method thereof, and storage medium storing writing method |
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- 1996-08-07 JP JP20858396A patent/JPH1055690A/en active Pending
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- 1997-08-07 US US08/908,673 patent/US5867427A/en not_active Expired - Lifetime
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Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
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US6094374A (en) * | 1998-03-25 | 2000-07-25 | Nec Corporation | Nonvolatile semiconductor memory device including sense amplifier having verification circuit |
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EP1074995A1 (en) * | 1999-08-03 | 2001-02-07 | STMicroelectronics S.r.l. | Method for programming multi-level non-volatile memories by controlling the gate voltage |
US6366496B1 (en) | 1999-08-03 | 2002-04-02 | Stmicroelectronics S.R.L. | Method for programming multi-level non-volatile memories by controlling the gate voltage |
US6185130B1 (en) * | 1999-10-18 | 2001-02-06 | Advanced Micro Devices, Inc. | Programmable current source |
US6498757B2 (en) * | 2000-11-23 | 2002-12-24 | Macronix International Co., Ltd. | Structure to inspect high/low of memory cell threshold voltage using current mode sense amplifier |
US20110063908A1 (en) * | 2001-04-27 | 2011-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile Memory, Verify Method Therefor, and Semiconductor Device Using the Nonvolatile Memory |
US7978531B2 (en) | 2001-04-27 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory |
US20040114444A1 (en) * | 2002-12-04 | 2004-06-17 | Sharp Kabushiki Kaisha | Semiconductor memory device and method for programming and erasing a memory cell |
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Also Published As
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JPH1055690A (en) | 1998-02-24 |
KR19980018610A (en) | 1998-06-05 |
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