JP3512336B2 - Non-volatile semiconductor multi-level storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device suitable for a flash memory for programming / erasing using Fowler-Nordheim tunnel current, and more particularly to storing information of 2 bits or more per memory cell. The present invention relates to a nonvolatile semiconductor multilevel storage device.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device,
A flash memory having the configuration shown in FIG. 18 is known.
In the following description, a reference numeral representing a terminal name also serves as a wiring name, a signal name, and, in the case of a power source, a voltage value thereof.

The configuration of the flash memory shown in FIG. 18 is based on the 1994 symposium
The Circuits Digest of Technical Papers, pp. 61-62 (1994 Symposium on VLSI Circ
uits Digest of Technical Papers, pp. 61-62). Writing and erasing to the memory cell are performed using Fowler-Nordheim tunnel current. FIG.
In the figure, reference numerals M11 to Mmn represent flash memory cells, and the source and drain are commonly connected every m memory cells. For example, the memory cell M1
1, M21 to Mm1, the sources of the memory cells are connected by the respective source diffusion layers to form the source s1, and the drains are connected by the respective drain diffusion layers to form the drain d1. With such a configuration, the number of contacts is reduced and the area of the memory cell is reduced. The MOS transistors MD1 to MDn and MS1 to MSn respectively include sources s1 to sn and drains d1 to dn and bit lines B1 to Bn or a common source line VN of m memory cells.
This is a switch MOS transistor connected to. NS
1 and NS2 are control signals for these switching MOS transistors. W1 to Wm are word lines, and WD
1 to WDm are word drivers. VH and VL are power supply terminals of the word drivers WD1 to WDm, and the chip has a plurality of groups each including the word drivers WD1 to WDm, and the voltage VH or VL corresponding to each group is selectively applied. . D1 to Dm are gate signal terminals of the word driver. The bit lines B1 to Bn are connected to circuits K1 to Kn including a sense circuit, an information holding circuit at the time of writing, and a write automatic verification circuit.

As described in the above-mentioned conventional example, by using the circuits K1 to Kn, the threshold voltage of each memory cell is set for every memory cell connected to one word line. Are in control. The IO connects the read signal of the bit line selected by the Y selection signals YS1 to YSn among the read signals appearing on the bit line to the amplifier in the subsequent stage, and the write information to the circuits K1 to Kn.
These are input / output signal lines that are selected by S1 to YSn and transferred.
In the figure, one input / output line IO is supplied with Y selection signals YS1 to YS.
Although the case of connecting by selecting by n is shown, a plurality of input / output lines IO may be provided and connected to a plurality of bit lines at the same time. MZ1 to MZn are MOS transistors that determine whether or not the states of all the memory cells are in the written state after the write verification. When all the bit lines B1 to Bn become the voltage VS after the write verification, the signal line A
No current flows through L.

In the flash memory having the above structure, the charge of the floating gate of each memory cell is injected or released by the tunnel current, and information is stored by the threshold voltage of the transistor at that time. Two values are selected as the threshold voltage and one bit of information is stored per memory cell. The flash memory cell of this conventional example has a so-called AND type configuration.

Regarding a flash memory for multi-valued storage, for example, 1995 IEE International Solid State Circuits Conference, pages 132 to 133 (1995 IEEE Interna
tional Solid-State Circuits Conference, pp.132-13
It is described in 3). The flash memory cell has a so-called NOR type configuration, in which hot electron injection is used for writing and Fowler-Nordheim tunnel current is used for erasing. In this conventional example, two stages of sense amplifiers and a plurality of dummy cells are provided in each of the input / output lines (IO lines) outside the memory cell array, and these are switched to switch the current according to the information when the word line is activated. Is being detected.

[0007]

However, in the flash memory shown in FIG. 18 of the conventional example described above, the degree of integration can be improved by devising a fine processing technique, but the process cost is high due to the miniaturization. There was a drawback that became. In order to solve this, so-called multi-value storage in which information of 2 bits or more per memory cell is stored can be considered. On the other hand, in the latter conventional example described above, the multi-valued flash memory of the NOR type configuration is realized by using a plurality of sense amplifiers for the input / output lines because it is configured to read in byte units. However, since, for example, 512 bytes are read in parallel at once, there is a problem in that the circuit scale becomes large if each bit line is provided.

Therefore, an object of the present invention is to perform both programming and erasing using the Fowler-Nordheim tunnel current as in the above-mentioned AND type conventional example, and for all memory cells connected to one word line. Another object of the present invention is to provide a nonvolatile semiconductor multi-valued storage device capable of storing multi-valued information of 2 bits or more, which is suitable for a flash memory configured to control the threshold voltage of each memory cell.

[0009]

In order to achieve the above object, in a nonvolatile semiconductor multi-value storage device according to the present invention, a memory cell has a floating gate and a control gate, and a tunnel phenomenon is used in the floating gate. In a non-volatile semiconductor multi-value storage device for storing and storing a plurality of bit information per memory cell by taking in and out charges, a voltage generating means for generating a plurality of voltages for reading and verification, and the voltage for a control gate of the memory cell. And a means for determining whether or not the memory cell has reached a desired threshold voltage based on the value of the current flowing through the memory cell at this time. It is a thing.

Further, in the nonvolatile semiconductor multi-valued memory device according to the present invention, the memory cell has a floating gate and a control gate, and charges are taken in and out from the floating gate by using a tunneling phenomenon, so that a plurality of memory cells are provided for each memory cell. In a nonvolatile semiconductor multilevel memory device that stores bit information, a plurality of dummy cells each having a different threshold voltage and a predetermined voltage is applied to the control gate of the memory cell to determine the current value flowing in the memory cell at this time. And a means for determining whether or not the memory cell has reached a desired threshold voltage based on the dummy cells.

Alternatively, in the nonvolatile semiconductor multi-valued memory device according to the present invention, the memory cell has a floating gate and a control gate, and charges are taken in and out of the floating gate by using a tunneling phenomenon, and a plurality of memory cells are provided per memory cell. In a nonvolatile semiconductor multilevel storage device that stores bit information, a plurality of sense latch circuits provided via a switch for each bit line and desired different threshold voltages connected to each sense latch circuit via a switch And a plurality of dummy cells each having
A predetermined voltage is applied to the control gate of the memory cell, and based on the current value flowing in the memory cell at this time, whether or not the memory cell has reached a desired threshold voltage is sequentially switched and connected to the sense latch circuit. The sense latch circuit may be configured to sequentially switch and connect the plurality of dummy cells for determination.

Further, in the nonvolatile semiconductor multi-valued memory device according to the present invention, the memory cell has a floating gate and a control gate, and charges are taken in and out by using a tunnel phenomenon in the floating gate, and a plurality of memory cells are provided for each memory cell. In a nonvolatile semiconductor multi-valued memory device for storing bit information, a sense latch circuit used for a binary read mode provided for each bit line, a plurality of dummy cells each having a different threshold voltage, and each dummy cell are selected. A multi-valued sense circuit used in a multi-valued read mode composed of a plurality of sense amplifiers for comparing and judging each threshold voltage of a memory cell, and the data output line are connected to the sense latch circuit and the multi-valued sense circuit by switching. Binary mode of burst read and random read with at least a plurality of switches It can be configured to be capable of switching the multi-level mode.

In any one of the nonvolatile semiconductor multi-valued memory devices described above, an operation of applying a write pulse for giving a voltage necessary for taking in and out the electric charge to each memory cell, and thereafter, the memory cell is set to a desired threshold voltage. The operation of verifying whether or not the voltage is applied based on the value of the current flowing through the memory cell at this time by applying a voltage to the control gate of the memory cell
As a cycle, when this write / verify cycle is repeated, the pulse width of the write pulse is set to increase as the write / verify cycle advances a predetermined number of times, or the absolute value of the pulse voltage of the write pulse is increased. It is preferable to set so that

Further, 1 corresponding to the plurality of bit information
It is preferable to set the Hamming distance between pieces of information corresponding to adjacent threshold voltages among the plurality of threshold voltages that can be set in the memory cell to the minimum.

In this case, the plurality of bit information is 2-bit information, and four threshold voltages which can be set in one memory cell corresponding to the 2-bit information are set in order from the lowest or the highest. Corresponding information is "00", "0"
You may set as 1 "," 11 ", and" 10 ".

Further, the threshold voltage of the memory cell after the irradiation of ultraviolet rays is the lowest of the lowest threshold voltage of the four threshold voltages that can be set, that is, the lowest threshold of the four threshold voltages. The lowest voltage within the variation range around the voltage, and the maximum voltage of the threshold voltage adjacent to this voltage, that is, 4
Between the maximum voltage within the variation range around the highest threshold voltage of the two, or between the maximum voltage of the highest threshold voltage and the lowest voltage of the adjacent threshold voltage. It is preferable to set so that.

Further, among the plurality of threshold voltages which can be set in one memory cell corresponding to a plurality of information, the threshold value when the Hamming distance between the information corresponding to adjacent threshold voltages is the largest. The threshold voltage of the memory cell after irradiation with ultraviolet rays may be set between the voltages.

In this case, the information of a plurality of bits is 2-bit information, and four threshold voltages which can be set in one memory cell corresponding to the 2-bit information are set in order from the lowest or the highest. Corresponding information is "00", "0"
In the case of 1 ”,“ 10 ”, and“ 11 ”, the threshold voltage of the memory cell after the ultraviolet irradiation is divided into the threshold voltage corresponding to“ 01 ”and the threshold voltage corresponding to“ 10 ”. Set it in between.

[0019]

According to the nonvolatile semiconductor multilevel memory device of the present invention, the voltage means for generating a plurality of voltages, that is, the word line voltage generation circuit VWG1 in FIG. The memory cell having the lowest threshold voltage among the plurality of threshold voltages of the memory cell corresponding to multi-valued information is determined by the first word line voltage from the lower one. Then, the memory cell having the next lower threshold voltage is determined by the second word line voltage. Similarly, a plurality of word line voltages are used according to the number of bits per memory cell. Alternatively, as shown in FIGS. 4 and 5, a plurality of dummy cells having a threshold voltage corresponding to an intermediate voltage of the threshold voltages of the written memory cells are provided and the current of the memory cells is Multi-valued information is read or verified by sequentially comparing.

At the time of writing, as shown in FIG.
Writing is performed on a memory cell having the highest threshold voltage (erased state) to verify whether or not it has been written, that is, whether the threshold voltage of the memory cell has reached a desired value is high. From the other side, it is determined whether or not the memory cell current flows by the first word line voltage. At this time, the memory cell whose lower threshold voltage is desired is also determined by the first word line voltage. As a result, all the memory cells whose threshold voltage should be determined by the first word line voltage and the memory cells whose threshold voltage is lower than this threshold voltage are determined by the first word line voltage. Becomes Next, writing is performed to a memory cell having a threshold voltage lower than the threshold voltage determined by the first word line voltage,
Whether the data has been written or not is determined by checking whether or not the memory cell current flows from the highest word line voltage according to the second word line voltage. At this time also, the memory cell having a threshold voltage lower than the threshold voltage determined by the second word line voltage is also performed at the same time. Similarly, the verification is performed using a plurality of word line voltages according to the number of bits per memory cell.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a nonvolatile semiconductor multilevel memory device according to the present invention will be described in detail below with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a circuit configuration diagram of a main portion showing a first embodiment of a nonvolatile semiconductor multilevel memory device according to the present invention. Incidentally, in FIG. 1, the same components as those of the conventional example shown in FIG. 18 will be described with the same reference numerals.

In this embodiment, word line voltage generation circuits VWG1 and VWG2, which are means for generating a plurality of word line voltages during read and write / verify operations, are provided. As a result, a plurality of bits can be read and written per memory cell, as will be described below. The word line voltage generation circuits VWG1 and VWG
The WG2 may also include a decoding function, in which case the voltage can be applied only to a specific set of word drivers. In particular, the word line voltage generation circuit VWG1 that generates a plurality of voltages is used for reading and verification, and the circuit configuration and the like will be described later. The word line voltage generation circuit VWG2 is a circuit that generates a negative voltage or a ground voltage during writing, and the internal power supply generation circuit disclosed in Japanese Patent Laid-Open No. 8-115599 previously filed by the applicant of the present application can be preferably used.

In FIG. 1, reference numerals SL1 to SLn are sense latch circuits, Vr is a reference voltage terminal, and PR is a signal for controlling a MOS transistor connecting the reference voltage terminal Vr and the sense latch circuits SL1 to SLn. In this figure, the automatic verification circuits and the like included in the conventional circuits K1 to Kn shown in FIG. 18 are omitted.

FIG. 2 is a diagram showing an operation example when reading multi-valued information by using the circuit configuration of the first embodiment shown in FIG. 1, (a) is a waveform diagram of word lines, and (b) is a waveform diagram. 8] is a diagram showing a threshold voltage distribution of memory cells and information corresponding to the threshold voltages. Here, as the multi-valued information, a case where each memory cell has 2 bits as shown in FIG. 2B will be described as an example. In this case, the threshold voltage of the memory cell has four possible cases V1 to V4, which have variations. Here, the threshold voltage is V1 when the information is "10", and V2 when the information is "11".
In the case of “01”, it is V3, and in the case of “00”, it is V4. With this setting, the Hamming distance of the information corresponding to the adjoining threshold voltage is 1, so that an error correction circuit configuration due to variations in the threshold voltage and retention (variation of the threshold when left unattended) There is a feature that you can easily.

In the present embodiment, the four threshold voltages V1 to V4 are read by using a plurality of word line voltages VR1 to VR3 as shown in FIG. First, the word line voltage is set to VR1. This word line voltage VR1 is shown in FIG.
As shown in (b), the memory cells whose threshold voltages are V2 to V4 are voltages that do not turn on. The information of the memory cell which is turned on by the word line voltage VR1 is "10", and the information of the memory cell which is not turned on has another value. This content is stored in a buffer on the memory chip or is taken out of the memory chip and stored.

Next, the word line voltage is set to VR2. The information of the memory cell turned on by the word line voltage VR2 is "1".
It becomes 0 ”or“ 11. ”This content is also stored in the buffer on the memory chip or taken out from the memory chip and stored. Finally, the word line voltage is set to VR3.
And The information of the memory cell turned on by the word line voltage VR3 becomes "10", "11" or "01",
The memory cell which is not turned on is "00".

By thus providing a plurality of word line voltages, a read operation for multilevel storage can be performed. The word line voltage starts from VR3 and starts from VR2 and V2.
You can do it in the order of R1, or start from VR2, etc.
Since the flash memory is non-volatile, the order can be changed. When storing information of 2 bits or more per memory cell, the types of voltage of the word line are increased.

An example of the operation of the circuit configuration of this embodiment shown in FIG. 1 is shown in FIG. 3 (a) as timing 1, FIG. 3 (b) as timing 2 following timing 1, and as shown in FIG. 3 (c). A timing chart showing timing 3 following 2 is shown in the timing chart. In FIG. 3, the word line W1 and the bit lines B1 to B4, and the Y selection signals YS1 and YS2, which are necessary for the description, are shown.
Shows only. The solid lines of the bit lines B1 and B2 show the voltage waveform of the bit line on the memory cell side of the sense latch circuit, and the dotted line shows the voltage waveform of the reference voltage Vr side of the sense latch circuit.

At timing 1 in (a), first, the bit lines B1 and B2 are precharged. After this, the word line W
The voltage of 1 is VR1. As a result, for example, a current flows in the memory cell M11 connected to the bit line B1 and the potential of the bit line B1 decreases. On the other hand, bit line B
No current flows in the memory cell M12 connected to 2, and the potential of the bit line B2 does not change. After this, this signal is sensed. As a result, a signal having an amplitude of about the power supply voltage is obtained on each of the bit lines B1 to Bn. After that, the Y selection signals YS1 and YS2 are sequentially turned on to turn on the bit lines B1 and B2.
The signal 2 is read. After reading all the signals, move to the next timing 2.

At timing 2 in (b), word line W1
The same read operation is performed by setting the voltage of 2 to VR2. At this time, the current also flows through the bit line B1 connected to the memory cell through which the current flows through the read operation at the word line voltage VR1. In this example, it is assumed that current flows in the memory cell M12 connected to the bit line B2. It is also assumed that no current flows through the bit line B3. Similar to the above, the bit line information is read by the Y selection signals YS1 and YS2.

At timing 3 in (c), the word line W1
Is set to VR3. The potentials of the bit lines B1 and B2 in which the current flows at the voltage VR2 decrease. Furthermore, here
It is assumed that a current starts flowing through the bit line B3. It is assumed that it did not flow to the bit line B4.

By the above operation, the information "10" is read from the memory cell M11 connected to the bit line B1, the information "11" is read from the memory cell M12 connected to the bit line B2, and the bit line is read. Memory cell M connected to B3
The information "01" is read from 13 and the bit line B4
This means that the information "00" is read from the memory cell M14 connected to.

Next, the write / verify operation of this embodiment will be described with reference to FIG. FIG. 9 is an explanatory diagram showing the write / verify operation, and shows a case where 2 bits are stored per memory cell (hereinafter abbreviated as cell). As shown in FIG. 2, each cell has four possible threshold voltage states. From the lowest threshold voltage, “10”, “11”,
Corresponds "01" and "00". In FIG. 9, there are four memory cells, and consider the case where 8-bit information is written in them. "00011110" is assumed as the data string. Since 2 bits are stored per cell, for example, "00" in cell 1, "01" in cell 2, "11" in cell 3,
"10" is written in the cell 4. That is, the cell 1 has the highest threshold voltage, the cells 2 and 3 have the lowest threshold voltages, and the cell 4 has the lowest.

First, as shown in (a) erasure of FIG.
All four cells are erased. The erased state is the state in which the threshold voltage is the highest and corresponds to information "00". In this state, the cell 1 to which "00" is written has a desired threshold voltage. The information to be written in cell 2, cell 3 and cell 4 corresponds to a lower threshold voltage.

Therefore, first, as shown in (b) Write 1, the write / verify operation is repeated for the three cells (cell 2, cell 3, cell 4) aiming at the threshold voltage corresponding to "01". . That is, the write voltage of the word line W is written by using the write word line voltage generation circuit VWG2, for example, −9V.
Then, for example, 0 V is applied to the drain of the cell 1 and 4 V is applied to the drains of the cells 2, 3 and 4 by a power source (not shown). As a result, the threshold voltage of the cell 1 does not change so much, but in the cells 2, 3, and 4, electrons are emitted from the control gate by the tunnel phenomenon, and the threshold voltage decreases. At this time, the word line voltage supplied from the word line voltage generating circuit VWG1 of the present embodiment at the time of verification corresponds to "01" because no current flows in the cell 1 having the threshold voltage corresponding to "00". In cells 2 to 4 having the threshold voltage, it is a voltage at which a current starts to flow. At the end of write 1, cell 2 has the desired threshold voltage.

Next, as shown in (c) Writing 2, the writing / verifying operation is repeated in the cells 3 and 4 aiming at the threshold voltage corresponding to "11". That is, the word line voltage generating circuit VWG2 is used to set the word line W to a write voltage, for example, -9V, 0V is applied to the drains of the cells 1 and 2, and 4V is applied to the drains of the cells 3 and 4. Add. This allows cells 1 and 2
Although the threshold voltage of the cell does not change much,
Threshold voltage is decreasing. At this time, as for the word line voltage at the time of verification supplied from the word line voltage generation circuit VWG1 of this embodiment, no current flows in the cells 1 and 2 having the threshold voltages corresponding to “00” and “01”. In cells 3 and 4 having a threshold voltage corresponding to “11”, this is a voltage at which a current starts to flow. This word line voltage is lower than the write 1 word line voltage. When writing 2 is completed, cell 3
Becomes a desired threshold voltage.

Finally, as shown in (d) Writing 3,
The write / verify operation is repeated in the cell 4 aiming at the threshold voltage corresponding to “10”. For example, 0V is applied to the drains of the cells 1, 2 and 3 by a power source (not shown), 4V is applied to the drain of the cell 4, and the word line voltage generating circuit VWG2 is used to write the word line W to a voltage for writing, for example. -9V. At this time, the word line voltage at the time of verification supplied from the word line voltage generation circuit VWG1 of the present embodiment is the current in the cells 1 to 3 having the threshold voltages corresponding to “00”, “01”, and “11”. Does not flow, and a current starts to flow in the cell 4 having the threshold voltage corresponding to “10”. This word line voltage is lower than the word line voltage at the time of writing 2. In this way, the threshold voltage of each cell can be set to a desired value. The word line voltage at the time of verification may use the same value.

As described above, the lower threshold voltages shown in FIG. 2 are associated with "10", "11", "01", and "00" to correspond to adjacent threshold voltages. Since the Hamming distance between data is 1, there is a feature that the circuit configuration for error correction becomes easy. In particular, the threshold voltage Vthi of the flash memory at the time of ultraviolet irradiation is the highest threshold voltage V4 in FIG. 2, that is, the threshold voltage corresponding to information is the highest, and this is near the voltage when electrically erased. In this case, it is preferable to set such a Hamming distance. This is because the electric charge in the floating gate at Vthi is in a thermal equilibrium state of this memory cell, and if the memory cell is left for a long time, the threshold voltage of the memory cell changes toward Vthi. Therefore, it is the memory cell having the threshold voltage of V1 in FIG. 2 that the phenomenon in which the threshold voltage increases when left alone is most likely to occur, and the phenomenon in which the threshold voltage increases next is likely to occur in V2. The memory cell has a threshold voltage of. If the Hamming distance is 1, the circuit configuration for error correction at this time becomes easy. As described above, one feature of the nonvolatile semiconductor multilevel memory device of the present invention is that the data is set so that the Hamming distance becomes 1 when Vthi is near the threshold voltage V4. Of course, the same idea is applied to bring Vthi near the lowest threshold voltage.

From the lower threshold voltage, that is, the threshold voltage V1 is "11", V2 is "10",
To associate "01" with V3 and "00" with V4,
The Hamming distance of information corresponding to the threshold voltages V2 and V3 is 2. However, the method of constructing this data divides the threshold voltage into low groups V1 and V2 and high groups V3 and V4,
The upper bits "1" and "0" are made to correspond to this, and the lower bit in each group is made to correspond to the lower voltage and "0" to the higher voltage. This is 2 per cell
This is a configuration method that is easily expanded to more than bits, and data can be easily coded and decoded. In this case, the threshold voltage Vthi in the thermal equilibrium state is set between the threshold voltages V2 and V3 having the Hamming distance of 2. In this case, since the voltage difference between Vthi and V2 and the voltage difference between Vthi and V3 are small, it is difficult for the threshold voltage to change when left unattended. Therefore, the possibility of erroneous data can be reduced.
The same is true when the "1" and "0" are interchanged, and it is also a feature of the nonvolatile semiconductor multilevel memory device of the present invention that Vthi is set while the Hamming distance is long.

As described with reference to FIG. 9, the threshold voltage is the lowest, "10", "11", "01", "0".
Since "00" corresponds to the erased state in writing when 0 is made to correspond, cell 1 which stores it does not receive writing, and when writing is divided into three times, cell 2 which stores "01" A cell 3 that stores “11” undergoes one write operation, and a cell 4 that stores “10” undergoes three write operations, which receives the write operation once. The control device for performing the above may be implemented by a microprocessor or the like on a chip different from the chip of the nonvolatile semiconductor multi-value storage device of the circuit of this embodiment, or may be provided on the chip of the circuit of this embodiment.

In the control device provided on the chip of the circuit of the present embodiment or on another chip, when both 2 bits are "0", no writing is performed, and at the first writing, any one of the information of 2 bits is written. In the case of "1", the write operation is performed, in the second write, the write is performed when the upper bit is "1", and in the third write, the lower bit is inverted, and the inverted result and the upper bit are both "1". If the write operation is performed in the case of "," the control device can be realized with a simple logic circuit.

This write operation will be described with reference to FIG. First, the data string “00011110” is divided into two bits, “00”, “01”, “11”, and “10”, which are set to the upper bit “0011” and the lower bit “01”.
For convenience, it is divided into 10 ″. The original data at this time may include a code for error correction.
Register A for upper bits and register B for lower bits
These data are stored in memory cells, for example, memory cells M11, M12, M13, M14 connected to the word line W1.
It is stored in association with. The data in this register is sensed by the sense latch SL1 while performing the simple operation as described above.
It may be stored in SL4. That is, in the first write, since any one of the 2-bit information is "1", the data is "0111" in the register A or B.
The second time is the case where the upper bit is "1", so the data of register A is "0011", and the third time is the case where the result of inverting the lower bit and the upper bit are both "1". It is data “0001” of and B (here, symbol “represents inverse”). By doing so, it is possible to write data in which the Hamming distance is all 1 which is the present invention.

FIG. 11 shows an example of the word line timing during the write / verify operation shown in FIGS. 9 and 10.
In the first example of (1), the word line voltage during writing is Vw.
And the pulse width is constant. At the time of verification, three types of voltages are required as described with reference to FIG. 9, and the voltages are Vv1, Vv2, and Vv3 from the highest voltage. That is, after erasing, writing is performed with a word line having a constant pulse width and a voltage of Vw, and it is verified whether or not the word line voltage of Vv1 is written in the second state from the highest cell threshold voltage. This writing and verification are repeated until all the cells to be written are written. Next, with a constant pulse width, V
The writing with the word line voltage of w and the verification with the voltage of Vv2 which is a voltage lower than the verification voltage Vv1 are repeated. As a result, the desired cell is written in the third state from the highest threshold voltage. Further, writing with a word line voltage of Vw with a constant pulse width and verification with Vv3 which is a voltage lower than Vv2 are repeated to write a desired cell up to the fourth state. The number of bits per cell is 3
In the case of bits, the same operation is performed for eight threshold voltages including the erased state, and in the case of 4 bits per cell, the same operation is performed for 16 threshold voltages including the erased state.

In the second example of (2), the word line voltage during writing is constant at Vw, but its pulse width is increased as the writing / verifying cycle progresses. That is, in the writing for verifying with the first verify voltage Vv1, after repeating the write / verify cycle several times with the first pulse width t11, the write / verify cycle is repeated several times with the pulse width t12 larger than t11. . Thereafter, the pulse width is similarly increased. In this way, the number of verification operations can be reduced as compared with the case where writing is repeated with a constant pulse width in a memory cell in which the threshold voltage is hard to change, that is, it is hard to write, and therefore the speed is increased. For example, after the write / verification cycle is repeated four times with the same pulse width, the pulse width is doubled.
In the writing for the verification with the next voltage Vv2, the first pulse width is t21 (in the drawing, the pulse width t21 is shown smaller than the previous pulse width t12 due to the space, but the previous verification voltage is t21. The pulse width is the same as or larger than the last write pulse width in the above (the same applies to the pulse width t31). In the write operation by the verification with the verification voltage Vv1, the pulse width is increased corresponding to the memory cell that is difficult to write at the end, so the pulse width t21 of the write word line voltage Vw at the verification voltage Vv2 is equal to the voltage. The pulse width may be equal to or larger than the last pulse width in the write operation by the verification with Vv1. This is because the threshold voltage of the cell in which writing is performed is already difficult to change with a short pulse width. Of course, the accuracy of threshold voltage setting can be increased by shortening it. Hereinafter, the pulse width is extended to t22 after a certain number of write / verify cycles, and the pulse width is extended as the write / verify further progresses.

As described above, the threshold voltage of the cell can be accurately controlled in each writing by gradually extending the pulse width from a small value each time a different threshold voltage is obtained. In addition, the number of verifications is significantly reduced as compared with the case of a constant pulse width, so that the writing speed becomes high.

Similarly, the write / verify operation for verifying with the voltage Vv3 is performed. At this time, the first pulse width of the write word line voltage Vw is t31. There is the same relationship between the pulse width t31 and the final pulse width in the write / verify cycle for verifying with the voltage Vv2 as in the method of setting the pulse width t21 described above. FIG. 12 is a flowchart showing the above processing. When the number of bits per cell is 3 bits, the threshold voltage is 8 including the erased state. When the number of bits is 4 bits, the threshold voltage is 16 including the erased state. Perform the same operation.

In the third example of (3) of FIG. 11, the word line at the time of writing is increased while increasing the pulse width from a small value for each constant pulse width or for each target threshold voltage as in the second example. The voltage also increases in absolute value as the writing / verifying cycle progresses. In writing by verification with the voltage Vv1,
The word line voltage starts from Vw11, and in the drawing, the word line voltage is increased to Vw12 in absolute value in the next cycle. Of course, the voltage may be changed to the voltage Vw12 after repeating the voltage Vw11 a certain number of times. By doing so, the threshold voltage can be written with high accuracy even in a cell in which writing is fast or a cell in which writing is slow due to variations in cell characteristics. Further, it is possible to reduce the tunnel current density of a cell in which writing is fast.

Next, in writing by verification with the voltage Vv2, the word line voltage is started from Vw21, and the word line voltage is changed to Vw22 after the next cycle or a fixed cycle.
Here, the word line voltage Vw21 is a value that is lower in absolute value than the final word voltage in the write / verify cycle for verifying with the verify voltage Vv1. In the write / verify cycle for verifying with the verify voltage Vv3, the word line voltage starts from Vw31, and the word line voltage is changed to Vw32 after the next cycle or a fixed cycle.

In the third example, it is also possible to increase the write pulse width as the write / verify cycle progresses, as in the second example of FIG. 11B. This is because, for example, when increasing the absolute value of the word line voltage, if there is a limit to increase the absolute value due to the relationship of disturbance, etc., write at the maximum word line voltage allowed by this absolute value instead of increasing the absolute value. The pulse width may be increased. FIG. 13 is a flowchart showing the above processing. When the number of bits per cell is 3 bits, the threshold voltage is 8 including the erased state. When the number of bits is 4 bits, the threshold voltage is 16 including the erased state. Perform the same operation. As described above, in the present embodiment, the multi-valued information can be accurately written in one cell by performing the writing / verifying as shown in FIGS.

Hereinafter, with reference to FIGS. 14 to 17, the read operation of FIG. 2 of the present embodiment and the write / write operation shown in FIGS. 9 and 10 will be described.
A plurality of word line voltage generation circuits used in the verification operation will be described. Incidentally, the write word line voltage generation circuit VWG2
Is the same as the internal power supply generation circuit of Japanese Patent Application Laid-Open No. 8-115599, so its explanation is omitted. FIG. 14 is a circuit diagram showing a configuration example of the word line voltage generation circuit VWG1 during the read or verify operation. In this circuit configuration, the three word line voltages VR1, VR2, VR3 described in FIG. 2 are generated in advance, and these three voltages are switched to the switches SWv1, S.
It is used by switching between Wv2 and SWv3. For generation of the verification voltage, another set of the same may be provided and connected in parallel with the output. Of course, the read voltage and the verify voltage may be the same. In this figure, there are internal power supply voltage circuits VP1, VP2, VP3, the gates of the output transistors M1, M2, M3 are connected to the operational amplifier AM based on the outputs of the reference voltage generation circuits VG1, VG2, VG3.
It is controlled by 1, AM2 and AM3. Internal power supply voltage circuit VP
1, VP2 and VP3 may be charge pump circuits or voltage lowering circuits. Also, two or more may be combined into one. With this configuration, it is possible to generate an internal power supply voltage required for multi-valued reading and verification of the present invention.

FIG. 15 is a circuit diagram showing another configuration example of the word line voltage generation circuit VWG1 at the time of read or verify operation. VP is an internal power supply voltage generating circuit, which generates a constant voltage. VG is a plurality of reference voltage generation circuits. The principle of the word line voltage generation circuit VWG1 is that the operational amplifier AM controls the output transistor M1 based on a plurality of voltages from the reference voltage generation circuit VG to generate a desired voltage from the constant voltage output of the internal power supply voltage generation circuit VP. It happens. M2 is a leak current MOS transistor, which is controlled by a control signal φ1. With this configuration, it is possible to generate a plurality of word line voltages necessary for this embodiment.

Next, FIG. 16 and FIG. 17 show configuration examples of the plurality of reference voltage generating circuits VG. In FIG. 16, BGG is a single reference voltage generation circuit, and a bandgap generator using a bipolar transistor and two types of MOS transistors of the same conductivity type having different threshold voltages are created and the voltage difference is used. Alternatively, there is a configuration in which flash memory cells having different threshold voltages are used and the voltage difference is used. As the bipolar transistor forming the bandgap generator, a parasitic bipolar transistor that can be used when forming a CMOS having a triple well structure can be used. Since the triple well structure is indispensable in the method of using the negative voltage for the word line, such a bipolar transistor can be easily formed. In FIG. 16, the output voltage of the single reference voltage generating circuit BGG and the VG
The output terminal voltage VR of is divided by the variable resistors R11 and R12 and input to the operational amplifier AM1 to control the output terminal voltage VR. The desired output terminal voltage VR can be generated by changing the values of the variable resistors R11 and R12. The variable resistors R11 and R12 are, for example,
This can be realized by connecting a plurality of switching MOS transistors having different resistance values connected in series and a plurality of sets of resistors having different resistance values in parallel and turning on which switching MOS transistor. This switching MOS transistor may be selected depending on the difference between reading and verifying and the threshold voltage of the cell. As a result, it is possible to generate a plurality of word line voltages required in this embodiment.

FIG. 17 shows another example of the reference voltage generating circuit VG. Unlike the case of FIG. 16, the output of one single reference voltage generation circuit BGG is set to three operational amplifiers A.
Input to M1, AM2 and AM3. Each operational amplifier uses different voltages for different modes (during reading and verification)
Occurs in. Taking the operational amplifier AM1 as an example, on the basis of the reference voltage generated by the single reference voltage generation circuit BGG, the switch SR is turned on at the time of reading to generate a voltage for controlling the resistance division between the resistors RR1 and R11, and at the time of verification, the switch is turned on. The SV is turned on to generate a voltage for controlling the resistance division of the resistors RV1 and R11. The same applies to the operational amplifiers AM2 and AM3, and based on the reference voltage generated by the single reference voltage generation circuit BGG, the resistors RR2 and RR3 are respectively read at the time of reading.
, And at the time of verification, the resistors RV2 and RV3 are used to generate desired voltages. The output of each operational amplifier is connected to the output terminal VR of the reference voltage generation circuit VG by switches SW1 to SW.
W3 is appropriately switched and connected.

<Embodiment 2> FIG. 4 is a circuit configuration diagram of a main portion showing a second embodiment of the nonvolatile semiconductor multilevel memory device according to the present invention. In this embodiment, two sets of sense latch circuits are provided for each of the bit lines B1 to Bn. Switch SW11
To sense latch circuits SL11 to SL connected by SWn1
n1 and sense latch circuits SL12 to SLn2 connected by switches SW12 to SWn2. here,
Based on the sense results of the first set of sense latch circuits SL11 to SLn1, the second set of sense latch circuits SL12 to SL12.
The operation of SLn2 is made different. That is, when the sense latch circuits SL11 to SLn1 of the first set operate by the current difference between the dummy cells DM11 to DMn1 having the threshold voltage of Vr1 and the memory cells M11 to Mnm, and the sensed result is determined, Pair of sense latch circuits SL12
~ Two types of dummy cells DM12 connected to SLn2 ~
DMn2 (threshold voltage is Vr2), dummy cell DM1
One of 3 to DMn3 (threshold voltage is Vr3) is selected for each sense latch.

Specifically, for example, the sense latch circuit SL
11, the node N11 is at the high level and the node N12
Is set to a low level and the switch is turned on at a high level, the switch S in the sense latch circuit SL12 is
W13 is off and switch SW14 is on.
Therefore, of the two types of dummy cells DM12 and DM13, the dummy cell DM12 is electrically connected to the sense latch circuit SL12. The dummy cell may be composed of a normal MOS transistor as shown in FIG. 4 to obtain a desired threshold value by adjusting the ion implantation concentration of the channel. Alternatively, the dummy cell may have a floating gate. Alternatively, writing may be performed so that the desired threshold voltage is obtained. Alternatively, the signals Sr1 to Sr3 are signals for controlling the dummy cells, but may be a desired threshold voltage depending on this voltage value. For example, it can be realized by preparing dummy cells having a floating gate structure for each kind of threshold voltage and transmitting the current value to the dummy cells DM11 to DM13 configured by a normal MOS transistor by a current mirror.

In FIG. 4, YS1 to YSn are switches for connecting the upper input / output line IOU and the lower input / output line IOD and the sense latch in accordance with the Y address information (this switch is the same as in the first embodiment described above). YS1 to Y shown in 1
It may be composed of MOS transistors like Sn)
CV is a conversion circuit that outputs binary information to the input / output line IO from the information of the upper and lower input / output lines IOU and IOD. Further, W1 to Wm are word lines, and MS1 to
MSn and MD1 to MDn are switching transistors that select a set of m memory cells, and these switching transistors are respectively control signals SD.
And SS.

FIG. 5 shows the principle by which multi-valued memory cell information can be read by the circuit of this embodiment configured as described above.
Will be explained. Now, the dummy cells DM11 to DMn
The threshold voltage of 1 is Vr1 and the dummy cells DM12 ...
The threshold voltage of DMn2 is Vr2, the dummy cell DM13
The threshold voltage of DMn3 is set to Vr3. And 2
In the case of a bit / cell (having a four-valued threshold voltage, the center value of which is lower from V1 to V4), the threshold voltage Vr1 is between the voltages V2 and V3, and the threshold voltage Vr2 is Between the voltages V3 and V4, the threshold voltage Vr3
Is set to be between V1 and V2. The threshold voltage is set as described above by adjusting the ion implantation concentration of the channel.

Now, referring to FIG. 4, a word line such as W1 is used.
Is selected and the control signals SD and SS are also selected so that the MOS transistor connected thereto is turned on. Here, the switches SW11 to SWn1 are turned on,
The control signal Sr1 is raised to set the dummy cells DM11 to DM.
Turn on n1. Since the threshold voltages of DM11 to DMn1 are Vr1, sense latch circuits SL11 to SL11 to
Using SLn1, the threshold voltage of the memory cell is V1,
It is determined whether the set is a set of V2 or a set of V3 and V4. Specifically, among the nodes N11 to Nn1, the high level one is a set of V3 and V4, and the nodes N12 to Nn2 are
The higher level of them is a set of V1 and V2. The sense latch circuit SL1 is, of course, which one it is.
1 to SLn1 are different.

Taking the sense latch circuit SL11 as an example, it is assumed that the node N11 has a high level and the node N12 has a low level. Therefore, the threshold voltage of the memory cell is V
3 or V4. Since the node N11 is at the high level, the switch SW14 is turned on, and the switch SW13 is not turned on because the node N12 is at the low level. Next, the switch SW11 is turned off, the switch SW12 is turned on, and the control signals Sr2 and Sr3 are set to the high level to turn on the dummy cell. Since the switch SW14 is turned on, the dummy cell DM12 and the memory cell are compared by the sense latch circuit SL12. Dummy cell DM
Since the threshold voltage of 12 is between V3 and V4, it can be determined whether the threshold voltage of the memory cell is V3 or V4. If the node N11 is low level and the node N12 is high level in the sense latch circuit SL11, the threshold voltage of the memory cell is V1 or V2. In this case, the switch SW13 is on and the switch SW14 is off. Therefore, the dummy cell DM13 having a threshold voltage of Vr3 is used. Since the threshold voltage Vr3 is between V1 and V2, the threshold voltage of the memory cell can be determined. The same applies to the two sets of sense latch circuits connected to other bit lines.

Thus, two sets of data corresponding to binary data are stored in the sense latch circuit. The conversion circuit CV converts this data into binary data. That is, when one of the Y selection switches YS1 to YSn is opened, if the input / output lines IOU and IOD are both at high level, the threshold voltage of the memory cell is V.
4 and the information "00" is output to the input / output line IO. When multi-valued information has 2 bits or more per cell, the number of sense latch circuits and dummy cells is increased, or data is transferred to the outside of the array and the lower information is read when upper information is determined. To go.

The above operation is shown in the timing chart of FIG. Note that the bit line precharge operation and the like are omitted in FIG. In the sense latch circuit, the node N1
1, N12, Nn1, N13, N23 and Nn3 are at high level, and nodes N12, N22, Nn2, N14 and N2
4, Nn4 is preset to low level.

First, the word line W1 and the control signal S
D and SS become high level, the information of the memory cell is read, the switch SW11 and the control signal Sr1 become high level, and the current signal of the memory cell and the current signal of the dummy cell are input to the sense latch circuit. Here, the sense latch circuit operates, and in the example of FIG. 6, the sense latch circuit SL11
Node N11 goes low and node N12 goes high. In the example shown in FIG. 6, the node N21 remains at the high level, the node N22 remains at the low level, the node Nn1 goes to the low level, and Nn2 also appears in other sense latch circuits according to the information of the memory cell. Will be at a high level. The switches SW11 to SWn1 are turned off, and the sense latch circuits SL11 to SLn1 are disconnected from the bit lines. As a result, the sense latch circuit stores information as to which of the two binary sets out of the possible threshold voltages of the four-valued memory cells.

Corresponding to this, the switches SW13, SW
24, SWn3 is turned on, and switches SW14, SW2
3, SWn4 turns off. By this, it connects with the dummy cell which can judge the binary threshold voltage in each group. In the example of FIG. 6, the word line W1 is once lowered. After the precharge operation of the bit lines not shown in the figure, the word line W1 is raised again, the switch SW12 is turned on, and the control signals Sr2 and Sr3 are raised. As a result, the current signal of the memory cell and the current signal of the dummy cell are input to the sense latch circuit SL12. Note that the word line W1 may be kept raised without being lowered once. Here, the sense latch circuit operates,
In the sense latch circuit SL12, the node N13 becomes low level and the node N14 becomes high level according to the information of the memory cell. In the example shown in FIG. 6, the node N23
Goes low, node N24 goes high, node Nn3 remains high and node Nn4 remains low. After this, switches SW12-SW
n2 is turned off, and the sense latch circuits SL12 to SLn2 are disconnected from the bit lines. As a result, information corresponding to the 2-bit data of the memory cell is stored in the two sets of sense latches per bit line. Next, as shown in FIG. 6, the Y selection switches YS1 to YSn are sequentially activated. A binary signal is output to the input / output line IO depending on the voltages of the input / output lines IOU and IOD at this time.

As described above with reference to FIGS. 4 to 6, multi-valued memory information can be read by providing two sets of sense latch circuits. Note that the sense latch circuit can be shared by a plurality of bit lines and can be used by switching with a switch.

The writing / verifying operation may be performed by the method shown in FIGS. 9 to 13 as in the first embodiment.

<Embodiment 3> FIG. 7 is a circuit configuration diagram of essential parts showing a third embodiment of the nonvolatile semiconductor multi-value storage device according to the present invention. In FIG. 7, Vr is a reference voltage when amplifying the information of the memory cell by the sense latch circuits SL1 to SLn, and as will be described later, this reference voltage Vr is used when the information of the memory cell is binary. Further, MA is a main amplifier circuit, and DB is an output buffer. DD
1 is a multi-valued sense circuit for reading multi-valued information,
SR1, SR2, and SR3 are switches that are turned on when the multi-valued sense circuit DD1 is used, and SS1 is a switch that is turned on when the multi-valued sense circuit DD1 is not used.

In this embodiment, multi-valued information is read using the multi-valued sense circuit DD1, but this reading method is essentially the same as that of the second embodiment. That is, the differential amplifier O
P1 is used to compare the read current of the dummy cell DM1 having the threshold voltage of Vr1 shown in FIG. 5 with the read current of the memory cell, and the possibility of the four-valued threshold voltage is first reduced to two. Switch SM2 or dummy cell DM3 connected to dummy cell DM2 using driver SK according to
The switch SM3 connected to is turned on to turn on the differential amplifier OP.
Either is judged in 2. The threshold voltage of the dummy cell DM2 is Vr2 shown in FIG.
The threshold voltage of M3 is Vr3 as shown in FIG. Thus, the result of the differential amplifier OP1 and the differential amplifier OP1
According to the result of 2, the conversion circuit CV generates corresponding binary data.

The difference from the second embodiment is that, for example, the word line W1 is selected, the Y selection switch YS1 is turned on, and the multi-valued information of only the memory cell M11 connected thereto is read out bit by bit or The point is that eight sets of multi-valued sense circuits DD1 and input / output lines IO and the like connected to them are provided to perform reading for each byte. In the first and second embodiments,
The memory cell information of all or part of the memory cells selected by one word line is first stored in a buffer such as a sense latch circuit, and then converted into binary data and output. Therefore, it takes 1 microsecond or more before the top data is output. On the other hand, the third
In the second embodiment, since the conversion is performed by the multi-valued sense circuit DD1, it is slower than the reading of binary data.
When the reading speed of the value data is 100 nanoseconds, 4
The reading speed of the value (2-bit) data is about 200 nanoseconds. Therefore, for example, even if the reading time of the entire data block is the same as in the first or second embodiment,
The read circuit configuration of this embodiment is effective when high-speed reading at the beginning is required for some applications.

In the circuit configuration of FIG. 7, when the data in the memory cell is binary, the sense latch circuits SL1 to SL1.
It can also serve as a circuit for reading once to SLn and then performing burst transfer. That is, as shown in FIG. 8, in the binary mode, burst read is performed, the switch SS1 is turned on, and the switches SR1 to SR3 are turned off. As a result, for example, the word line W1 is selected, the information of the memory cells M11 to Mn1 selected thereby is stored in the sense latch circuits SL1 to SLn, amplified in order by the main amplifier MA, and output terminal Do by the output buffer DB. The read information is output to.

On the other hand, in the multi-value mode, as shown in FIG. 8, random bit or byte reading is performed and the switch SS1 is turned off. Also, the switches SR2 and SR3 are turned on, the multi-valued sense circuit DD1 is used to read using the dummy cell DM1, the switch SR2 is turned off, and the switch SR1 is turned on to read the dummy cell DM2.
Alternatively, the multi-valued reading described above is performed using DM3. The result is converted into binary data by the conversion circuit CV, amplified by the main amplifier MA, and read information is output to the output terminal Do by the output buffer DB. Although switching to binary burst read is performed in FIG. 7, switches SR1 to SR3 and SS1 similar to those in FIG. 7 are provided in the input / output lines IOU and IOD of the circuit of the second embodiment to provide multi-valued data. By connecting the sense circuit DD1, it is possible to switch to the method of reading multi-valued information in this embodiment. In FIG. 7, the control signal line GM is a signal for turning on the dummy cells DM1, DM2, DM3, and the dummy cells DM1, DM
2, the source of DM3 is connected to the ground voltage VS. Also in this embodiment, the write / verify operation may be performed by the method shown in FIGS. 9 to 13 as in the first embodiment.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the spirit of the present invention. Is.

[0073]

As is apparent from the above-described embodiments, according to the present invention, a plurality of word line voltage generation circuits capable of generating a plurality of voltages used for reading and verification, or a plurality of dummy cells and a plurality of sense latch circuits are provided for each bit line. By providing, it is possible to realize reading and writing of multi-valued storage in a flash memory in which writing and erasing are performed by using Fowler-Nordheim tunnel current. Also,
By setting the Hamming distance of information for adjacent threshold voltages to 1, the circuit configuration for correcting a write error of multi-valued data becomes easy.

[Brief description of drawings]

FIG. 1 is a main part circuit diagram showing a first embodiment of a nonvolatile semiconductor multi-value storage device according to the present invention.

2A and 2B are explanatory views showing an example of a read operation of the nonvolatile semiconductor multi-valued memory device shown in FIG. 1, in which FIG. 2A is a word line voltage waveform diagram, and FIG. 2B is a memory cell read at this word line voltage. 3 is a threshold voltage distribution diagram of FIG.

FIG. 3 is a timing chart showing an operation example of the first exemplary embodiment.

FIG. 4 is a main-portion circuit diagram showing a second embodiment of the nonvolatile semiconductor multi-value storage device according to the present invention.

5 is a principle explanatory diagram of a read operation of the nonvolatile semiconductor multi-valued storage device shown in FIG. 4, and is a threshold voltage distribution diagram of dummy cells and threshold voltages of memory cells.

FIG. 6 is a timing chart showing an operation example of the second exemplary embodiment.

FIG. 7 is a main part circuit diagram showing a third embodiment of the nonvolatile semiconductor multi-value storage device according to the present invention.

FIG. 8 is a diagram of the nonvolatile semiconductor multilevel memory device 2 shown in FIG.
It is a figure which shows one read-out operation example.

9 is a diagram showing a write / verify operation example of the nonvolatile semiconductor multi-value memory device shown in FIG. 1;

10 is an explanatory diagram showing a method of writing data in which the Hamming distance is 1 in the nonvolatile semiconductor multilevel memory device shown in FIG. 1;

11 is a diagram showing an example of word line timings at the time of writing / verifying three types of the nonvolatile semiconductor multi-valued memory device shown in FIG. 1, where (1) is a case where the word line voltage and the write pulse width are constant. , (2) is a case where the word line voltage is constant and the write pulse width is increased, and (3) is a case where the word line voltage is increased and the write pulse width is constant.

12 is a diagram showing a flow example of the write operation of (2) shown in FIG.

13 is a diagram showing a flow example of the write operation of (3) shown in FIG.

FIG. 14 is a main part circuit diagram showing an example of a word line voltage generation circuit at the time of read and verify operations used in the nonvolatile semiconductor multi-value storage device shown in FIG. 1.

FIG. 15 is a main part circuit diagram showing another example of the word line voltage generation circuit at the time of read and verify operations used in the nonvolatile semiconductor multi-value storage device shown in FIG. 1.

16 is a main part circuit diagram showing an example of a variable reference voltage generation circuit used in the word line voltage generation circuit shown in FIG.

17 is a main part circuit diagram showing another example of the variable reference voltage generation circuit used in the word line voltage generation circuit shown in FIG. 15. FIG.

FIG. 18 is a main-portion circuit diagram showing a conventional example of a nonvolatile semiconductor memory device.

[Explanation of symbols]

CV ... Conversion circuit, M11-Mmn ... Memory cell, MS1-MSn, MD1-MDn ... Selection transistor, W1-Wm ... Word line, B1-Bn ... Bit line, SL1-SLn, SL11-SLn2 ... Sense latch circuit, K1 -Kn ... Information holding and verification circuit, VWG1, VWG2 ... Word line voltage generation circuit, VG ... Reference voltage generation circuit, DD1 ... Multi-valued sense circuit, VR1-VR3 ... Multi-valued read / verification word line voltage, Vr1-Vr3 ... Multi-value read / verify reference voltage.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-169284 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/02

Claims (21)

(57) [Claims] 1. A memory cell array having a plurality of memory cells having floating gates, and a write circuit for performing a first write operation and a second write operation executed after the first write operation, Since the threshold voltage of the memory cell stores at least ternary information in the memory cell depending on the amount of charge injected into the floating gate, the erased state, the second state, the erased state and the erased state are stored. The write circuit takes one of the values of the first state located between the second state and the write circuit, and in each of the write operations,
First means for applying a plurality of pulses to a connected word line
When, in the first write operation, the threshold voltage of the memory cell is threshold voltage in the erased state first
Each threshold voltage of the second Memorise Le a first memory cell and the threshold voltage to be a transition to a state to be transited to the second state to transition to the first state, in the second write operation, the threshold voltage of the second Memorise Le These types SL have been the first and second memory cell transitions to the first state and a second means for Ru to transition to the second state, said first means At the same timing of the first write operation,
And a pulse having the same amplitude and the same width is applied to the second memory cell, and in at least one of the write operations, the amplitude of the plurality of pulses is written.
Both of them are made larger, and the second means sets the bit line to the memory cell to be written.
Write to memory cells and sense latches connected through
Playback using the upper and lower bits of 2-bit data
The calculation is performed and the calculation result is stored in the sense latch.
And a first step in the first write operation.
And the sense latch connected to the second memory cell as described above.
The first data, which is the calculation result, should remain in the erased state.
The above operation is applied to the sense latch connected to the third memory cell.
The calculation result is different from the first data which is the result.
The second data is stored in each of the second data
And a sense latch connected to the second memory cell
The first data, which is the calculation result, is
The above operation result is connected to the sense latch connected to the third memory cell.
The second data, which is the result, is stored in each of the
The switch stores the first data, which is the above calculation result.
Output the first potential to the bit line,
The above bit when the second data which is the result is stored
A non-volatile semiconductor multi-value storage device, which outputs a second potential different from the first potential to the line . 2. A memory cell array having a plurality of memory cells each having a control gate and a floating gate, a first write operation, a second write operation executed after the first write operation, and the second write operation. And a write circuit that executes a third write operation performed after, the threshold voltage of the memory cell depends on the amount of charge injected into the floating gate of the memory cell. Of the first state, the second state, the third state, and the fourth state, which are erased states, the second state is between the first state and the third state. In addition, the third state is set between the second state and the fourth state, and in the write circuit , the write target memory cell is
First means for applying a plurality of pulses to a connected word line
When, in the above-described first write operation, and the second memory cell sac Chishi threshold voltage threshold voltage is in the first state
The first memory cell to be a transition to the state, the threshold value of the third memory cell and the second memory cell and the threshold voltage to transition the threshold voltage to the third state to be transited to the fourth state The voltage is transited to the second state, and in the second write operation, the second and third memory cells among the first, second and third memory cells transited to the second state . the memory cell Works threshold voltage to transition to the third state, in the third write operation, Qian to the third state
The said third memory cell Works threshold voltage of the transferred the said second and third memory cell Ru to transition to the fourth state
And the first means has the same timing of the first write operation.
In the same manner, pulses having the same amplitude and the same width are applied to the first, second and third memory cells, and at the same timing of the second write operation, the second
And a pulse having the same amplitude and the same width is applied to the third memory cell, and in at least one of the write operations, the amplitudes of the plurality of pulses are written.
Both of them are made larger, and the second means sets the bit line to the memory cell to be written.
Write to memory cells and sense latches connected through
Playback using the upper and lower bits of 2-bit data
The calculation is performed and the calculation result is stored in the sense latch.
In the first write operation,
Sense latch connected to first, second and third memory cells
The first data which is the above calculation result is
For the sense latch connected to the fourth memory cell
The calculation different from the first data which is the calculation result
The second data, which is the result, is stored respectively, and the second writing is performed.
Connected to the second and third memory cells in
The above-mentioned first data which is the above-mentioned operation result in the sense latch
Are connected to the first and fourth memory cells.
The above-mentioned second data, which is the above-mentioned calculation result, are stored in the respective switches.
Then, in the third write operation, the third memory cell
Which is the result of the above calculation in the sense latch connected to
Connect the first data to the first, second and fourth memory cells.
The second sensed result which is the above-mentioned calculation result is added to the sense latch to be continued.
The sense latch stores the data and the sense latch stores the operation result.
The above bit when the first data, which is the result, is stored
The first potential is output to the line, and the second data, which is the calculation result, is output.
Data is stored in the bit line, the first potential is applied to the bit line.
Outputs a different second potential from the non-volatile semiconductor multi-value storage device. 3. The nonvolatile semiconductor multi-value storage device according to claim 1, wherein in each of the write operations, the amplitudes of the plurality of pulses are increased as the write progresses . Wherein said at least one of a write operation of the write operation, the previous one of the plurality of pulses
The amplitude of the line pulse is, non-volatile semiconductor multilevel memory device according to claim 1 or 2, characterized in that it is smaller than the amplitude of the applied pulse after. 5. In each of the write operations, the amplitude of the preceding pulse of the plurality of pulses is marked after that.
4. The nonvolatile semiconductor multilevel storage device according to claim 3, wherein the amplitude is smaller than the applied pulse amplitude. 6. The non-volatile semiconductor multi-value storage device according to claim 1, wherein a pulse having the same amplitude is continuously applied to each of the write operations. 7. A nonvolatile semiconductor multilevel according to any one of claims 1 to 6 at least a plurality of pulse widths used in any of the write operation of the write operation, characterized in that the same Storage device. 8. A nonvolatile semiconductor multilevel according to any one of claims 1 to 6, characterized in that the width of the plurality of pulses used in at least one of a write operation of the write operation is increased gradually Storage device. 9. A memory cell array having a plurality of memory cells having floating gates, and a write circuit for executing a first write operation and a second write operation executed after the first write operation, Since the threshold voltage of the memory cell stores at least ternary information in the memory cell depending on the amount of charge injected into the floating gate, the erased state, the second state, the erased state and the erased state are stored. The write circuit takes one of the values of the first state located between the second state and the write circuit, and in each of the write operations,
First means for applying a plurality of pulses to a connected word line
In the first write operation, the threshold voltage of the memory cells whose threshold voltage is in the erased state is set to the first threshold voltage.
Each threshold voltage of the second Memorise Le a first memory cell and the threshold voltage to be a transition to a state to be transited to the second state to transition to the first state, in the second write operation, the threshold voltage of the second Memorise Le These types SL have been the first and second memory cell transitions to the first state and a second means for Ru to transition to the second state, the first The means is configured to perform the first write operation at the same timing of the first write operation .
And a pulse having the same amplitude and the same width are applied to the second memory cell, and when the writing progresses within the width of the plurality of pulses in at least one of the writing operations,
And the second means adds a bit line to the memory cell to be written.
Write to memory cells and sense latches connected through
Playback using the upper and lower bits of 2-bit data
The calculation is performed and the calculation result is stored in the sense latch.
And a first step in the first write operation.
And the sense latch connected to the second memory cell as described above.
The first data, which is the calculation result, should remain in the erased state.
The above operation is applied to the sense latch connected to the third memory cell.
The calculation result is different from the first data which is the result.
The second data is stored in each of the second data
And a sense latch connected to the second memory cell
The first data, which is the calculation result, is
The above operation result is connected to the sense latch connected to the third memory cell.
The second data, which is the result, is stored in each of the
The switch stores the first data, which is the above calculation result.
Output the first potential to the bit line,
The above bit when the second data which is the result is stored
A non-volatile semiconductor multi-value storage device, which outputs a second potential different from the first potential to the line . 10. A memory cell array having a plurality of memory cells having a control gate and a floating gate, a first write operation, a second write operation executed after the first write operation, and the second write operation. And a write circuit that executes a third write operation performed after, the threshold voltage of the memory cell depends on the amount of charge injected into the floating gate of the memory cell. Of the first state, the second state, the third state, and the fourth state, which are erased states, the second state is between the first state and the third state. In addition, the third state is set between the second state and the fourth state, and in the write circuit , the write target memory cell is
First means for applying a plurality of pulses to a connected word line
When, in the above-described first write operation, and the second memory cell sac Chishi threshold voltage threshold voltage is in the first state
The first memory cell to be a transition to the state, the threshold value of the third memory cell and the second memory cell and the threshold voltage to transition the threshold voltage to the third state to be transited to the fourth state The voltage is transited to the second state, and in the second write operation, the second and third memory cells among the first, second and third memory cells transited to the second state . the memory cell Works threshold voltage to transition to the third state, in the third write operation, Qian to the third state
The said third memory cell Works threshold voltage of the transferred the said second and third memory cell Ru to transition to the fourth state
And a second means, said first means, at the same timing of the first write operation, by applying a same amplitude, the same width of the pulse to the first, second and third memory cells, the At the same timing of the second write operation, the above second
And a pulse having the same amplitude and the same width is applied to the third memory cell, and when the writing progresses within the width of the plurality of pulses in at least one of the writing operations,
And the second means adds a bit line to the memory cell to be written.
Write to memory cells and sense latches connected through
Playback using the upper and lower bits of 2-bit data
The calculation is performed and the calculation result is stored in the sense latch.
In the first write operation,
Sense latch connected to first, second and third memory cells
The first data which is the above calculation result is
For the sense latch connected to the fourth memory cell
The calculation different from the first data which is the calculation result
The second data, which is the result, is stored respectively, and the second writing is performed.
Connected to the second and third memory cells in
The above-mentioned first data which is the above-mentioned operation result in the sense latch
Are connected to the first and fourth memory cells.
The above-mentioned second data, which is the above-mentioned calculation result, are stored in the respective switches.
Then, in the third write operation, the third memory cell
Which is the result of the above calculation in the sense latch connected to
Connect the first data to the first, second and fourth memory cells.
The succeeding sense latch continues to the second data
The sense latch stores the data and the sense latch stores the operation result.
The above bit when the first data, which is the result, is stored
The first potential is output to the line, and the second data, which is the calculation result, is output.
Data is stored in the bit line, the first potential is applied to the bit line.
Outputs a different second potential from the non-volatile semiconductor multi-value storage device. 11. The each write operation, the nonvolatile semiconductor multilevel memory device according to claim 9 or 10, characterized in that is increased along with the write widths of the plurality of pulses travel. 12. The write operation of at least one of the write operations, wherein:
The width of the preceding pulse, the non-volatile semiconductor multilevel memory device according to claim 9 or 10, characterized in that less than the width of a pulse applied to a later. 13. The width of a preceding pulse of the plurality of pulses is smaller than the width of a pulse applied after that in each of the write operations.
11. The nonvolatile semiconductor multilevel storage device according to item 11 . 14. A each write operation, the nonvolatile semiconductor multilevel memory device according to any one of claims 9 to 11, characterized in that there is a portion where the pulse of the same width is applied continuously. 15. The first pulse width of the second write operation
The nonvolatile semiconductor multilevel memory device according to any one of claims 9 to 14, characterized in <br/> be the first or last pulse width of the write operation. 16. The first pulse width of the second write operation.
And the first or last pulse width of the write operation,
The first pulse width of the third write operation is set to the second pulse width .
Nonvolatile semiconductor multilevel memory device according to any one of claims 9 to 14, characterized in that the above last pulse width of the write operation. 17. The nonvolatile semiconductor multilevel according to any one of claims 9 to 16 the amplitude of a plurality of pulses used in at least one of a write operation of the write operation, characterized in that the same Storage device. 18. The non-volatile semiconductor multilevel according to any one of claims 9 to 16, wherein the amplitude of the plurality of pulses used in at least one of a write operation of the write operation is increased gradually Storage device. 19. A verify operation for checking the state of the memory cell is performed each time each pulse is applied during the operation of applying the plurality of pulses, and the verify operation applies a predetermined verify voltage pulse to the memory cell. nonvolatile semiconductor multilevel memory device according to any one of claims 1 to 18, characterized in that is carried out by applying to. 20. A verify operation for checking the state of the memory cell is performed each time each pulse is applied during the application operation of the plurality of pulses, and the verify operation applies a predetermined verify voltage pulse to the memory cell. The plurality of verify voltage pulses applied during the first write operation are set to have a first amplitude, and the plurality of verify voltage pulses applied during the second write operation are applied. 19. The nonvolatile semiconductor multi-value storage device according to claim 1, wherein the amplitude is set to a second amplitude, and the first amplitude and the second amplitude are different. 21. A verify operation for checking the state of the memory cell is performed each time each pulse is applied during the operation of applying the plurality of pulses, and the verify operation applies a predetermined verify voltage pulse to the memory cell. The plurality of verify voltage pulses applied during the first write operation are set to have a first amplitude, and the plurality of verify voltage pulses applied during the second write operation are set to a first amplitude. The amplitude is set to a second amplitude, and the amplitudes of a plurality of verify voltage pulses applied during the third write operation are set to a third amplitude, the first amplitude, the second amplitude, and the second amplitude. 3 of amplitude nonvolatile semiconductor multilevel memory device according to any one of claims 2 to 8 and 10 to 18, wherein different.