JPS6070597A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To keep the value of writing current almost constant by changing the gate voltage of a write control MOS TR or column selecting MOS TR in accordance with the value of the writing current. CONSTITUTION:A high voltage VP due to a decoded output X is impressed to the gate of a memory cell 11 and injected into an electron floating gate at the generation of impact ionization to write data. At that time, large current is made to flow into a course consisting of a resistor 21, MOS TRs 13, 12 and the memory cell 11. When the current is made to flow into the resistor 21, a potential difference is generated between both the ends of the resistor 21 and a voltage VA smaller than the VP is obtained from a serial node 22. If the current flowing into the resistor 21 is constant, the voltage VA is also constant, output voltage VB from a control circuit 30 is also fixed and the ON resistance value of the MOS TR13 is also fixed, so that the constant current is kept as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a non-volatile semiconductor device having a data writing circuit.

[Technical background of the invention]

Non-volatile semiconductor memory devices, especially floating-gate structure MO
In a memory device that uses S-tran nostar as a memory cell, data 0" and "1" are stored depending on whether deuterons are injected into the floating dirt of the memory cell or whether the injection type remains in a neutral state. The memory cell is "0".

1''data'f: When programming data when burning a memory, high voltage is selectively applied to the dirt and drain of the memory cell in order to write the same data to the state in which electrons have been injected. .

FIG. 1 is a circuit diagram schematically showing the configuration of a data write-in circuit portion of a conventional nonvolatile semiconductor memory device. In FIG. 1, reference numeral 11 denotes a memory cell having a floating dart structure, in which decoded output X from a row decoder is input as a dart. The source of this memory cell 11 is ground'
Connected to a potential point. Reference numeral 12 denotes a column selection MOS transistor υ, to whose gate, for example, a decode output Y from a column decoder is input. Reference numeral 13 denotes a MOS transistor for cooling control, and the output data D from the input circuit 14 is input to its dart. The drain and north terminals of the two MOS transistors 12 and 13 are inserted in series between the voltage VPO application point for data writing and the drain of the memory cell 11. The input circuit 14 is driven by a voltage VC smaller than the voltage VP, and a g/D type inverter 15 is provided to sequentially invert input data Din.
．． 16. An E/D type inverter 17 is driven by the voltage V and is provided to invert the output of the inverter 1G, and a program i is connected between the output terminal of the inverter 17 and the ground potential point. -v PGM
It is composed of a MOS transistor 18 controlled by a MOS transistor 18. Then, the output of the inverter 17 is input as the data D to the dart of the MOS transistor 13. Furthermore, the series connection point 19 of the MOS transistors 12 and 13 is connected to the input end of a sense amplifier (not shown).

In such a configuration, when the input data D at the 0'' level is supplied to the input circuit 14, the Zologram No. 4M PGM is set at the 0'' level. At this time, the MOS transistor 18 is turned off by the signal PGM, and the output data D is set to the "1" level, that is, the voltage vP.

Now, when data is written to the memory cell 11 in FIG. 1, the decode outputs X and Y are both set to the madder voltage vP. By setting the output data D and the decode output Y from the input circuit 14 to vP, the MOS l-rannostar 13 for write control and the MOS for column selection
Transistor 12 is turned on, thereby applying high voltage vP to the drain of memory cell 11.

As a result, a high pressure vP is applied to both the dirt and the drain of this memory cell 11, so that electron and hole pairs are generated in this memory cell 11 due to ink ionization. , among which electrons are injected into the floating darts to write data. That is, when writing data, a large current flows through the memory cell 11 using the two MOS transistors 13 and 12 as load circuits.

FIG. 2 shows the memory cells 11 and M in the circuit shown in FIG.
FIG. 2 is a curve diagram showing the voltage-current characteristics of each of the load circuits including the lannostars 13 and 12. The curve A in FIG. 2 is for the memory cell 1, and the curve opening is for the load circuit. The voltage at the intersection of the two curves A and 1 is the drain voltage VD of the memory cell 1, and the current is the drain current ID.

[Problems with background technology]

By the way, in such a conventional circuit, the value of the current flowing through the memory cell changes due to variations in the channel length of the memory cell. However, when the channel length of a memory cell becomes shorter, its voltage-current characteristic curve changes from A to C in FIG. That is, as the channel length becomes shorter, a larger current flows even with a smaller drain/voltage, and the point of intersection with the characteristic curve of the load circuit moves toward the larger ID. If the drain ftMtLpO difference of the memory cell when the channel length changes is ΔI, then in a 1-bit memory cell, the write tL current increases by ΔI. In a storage device, data is written or read in units of one word, which is made up of multiple bits.For example, if one word is made up of 8 bits, 8・ΔI
An increase in current occurs. It is known that the shorter the channel length of a memory cell, the faster writing can be performed. However, if the channel length is short,
Since the write current increases rapidly as described above, the channel length cannot be made very short. Because the write current is highly dependent on the channel length of the memory cell, traditional memory devices have the disadvantage of narrowing process margins because the channel length of the memory cell must be carefully controlled. be.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to allow a nearly constant write current to flow regardless of the channel length of the memory cell, thereby widening the process margin. The object of the present invention is to provide a nonvolatile semiconductor memory device that is possible.

[Summary of the invention]

In the non-volatile semiconductor memory device according to the present invention, the value of the write current flowing through the memory cell is determined by converting the voltage of the MOS (MOS) transistor for write control or the 1VIO8) transistor for column selection, which serves as the load circuit of the memory cell, into the value of the write current flowing through the memory cell. The value of the write current is kept almost constant by changing the current value according to the current value.

[Embodiments of the invention]

An embodiment of this emission ψ] will be described below with reference to the drawings. FIG. 3 is a circuit diagram schematically showing the configuration of the data write circuit portion of the nonvolatile semiconductor memory device according to the present invention. In order to clarify the explanation, the same reference numerals used in FIG. 1 will be used for the parts corresponding to the conventional circuit in FIG. 1. In FIG. 3, 11 is a memory cell, 12
13 is a MOS transistor for column selection, 13 is a MOS lannostar for write control, and 14 is an input circuit. In this embodiment circuit, a resistor 21 is newly inserted between the MOS transistor 13 and the point of application of the high voltage vP for writing.

Furthermore, in this embodiment circuit, a control circuit 30 is newly provided. One side of this control circuit consists of the resistor 21 and the MO
8) Detect the '1 voltage V person at the series connection point 22 with the lannostar 13, and apply the voltage VB corresponding to this voltage vA to the M
O8) This circuit 30 is used to supply the dirt of the Nostar 13, and this circuit 30 is constructed as follows. High voltage V.

There is a threshold voltage V between the application point and the ground potential point.
A MOS transistor 3 whose th is set approximately near Ov and another MOS transistor 32 are connected in series, and the gate of the MO8) run raster 3 is connected to the series connection point 22. There is. Similarly, two MOS transistors 33 and 34 are connected in series between the high voltage vP application point and the ground potential point, and the gate of the MO8 transistor 33 is connected to the high voltage vP application point. Furthermore, the dart of the MO8 transistor 34 is connected to the series connection point 35 of the two MOS transistors 37 and 32, and the dart of the MO8) lannostar 32 is connected to the series connection point 35 of the two MOS transistors 33 and 34. It is connected to the. In addition, a desorption type MOS is connected between the high voltage vP application point and the ground potential point.
Transistor 37 and another MOS transistor 38
The MOS transistor 39 and another MOS transistor 40 are connected in series, respectively. The dart of the transistor 39 is connected in series with the series connection point 36. Above MO8) transistor 40
The dart is connected to the series connection point 4 of the two MOS transistors 37 and 38, and the dart of the MOS transistor 38 is connected to the series connection point 42 of the two MOS transistors 39 and 40, respectively. The voltage at the series connection point 4 is supplied to the MOS transistor 13 as the '1B voltage VB. On the other hand, the output data D from the input circuit 14 is inverted by an E/D type inverter 45 consisting of a depletion type MOS transistor 43 and an enhancement type MOS transistor 44, and the inverted data D is output from the control circuit 14. MOS transistor 4 connected between series connection point 4, which is the output end of voltage VB, and the ground potential point.
It is supplied to 6 cases. In the embodiment shown in FIG. 3, all of the MOS transistors whose type is not specified are of the encoder type.

Next, the effect will be explained. Now, when data is written to memory cell 1 in FIG. 3, both decode outputs X and Y are set to high voltage vP.

Also, at this time, input data Din of "0# level" is supplied to the input circuit 14, and the program signal PGM is "0#".
Since the output data D from the input circuit 14 is set to the I+ level, the output data D from the input circuit 14 is set to the "'l#" level, and the output data of the Inno R-Y 45 is set to the "0" level and the MO
S transistor 46 is turned off. That is, at this time, the second MOS transistor 13 is connected to the control circuit 30 (
Controlled by D output voltage VB. Now, this MOS transistor 13 has its on-resistance set to a relatively small value by the voltage VB. In this case, a high voltage slightly smaller than vP is applied to the drain of memory cell 1). Since a high voltage VP due to the decode output X is applied to the dirt of the memory cell 11, electrons are injected into the floating case due to the occurrence of impact ionization as described above, and r-tar writing is performed. It will be done. When writing this data, a large current flows through the path of the MOS transistor 13, 12 of the resistor 21 and the memory cell 11. The value of the current at this time is held constant for the following reasons. That is, as a result of the current flowing through the resistor 2, a potential difference is generated between both ends of the resistor 2, so that a voltage V^, which is smaller than V, is obtained at the series connection point 22. If the current flowing through the resistor 2 is constant, the voltage VA is also constant, and the output voltage Va from the control circuit is also constant.
As a result, the on-resistance value of the MOS transistor 13 also becomes constant, so that the above-mentioned constant current can be maintained as it is.

If a variation occurs in the channel length of the memory cell 11 and, for example, the channel length becomes shorter, a larger write current will flow through the memory cell 11 than before. An increase in the write current in the memory cell 11 causes an increase in the current in the resistor 21, which causes the spot pressure vA to become smaller than before. Now, in the control circuit, when the voltage difference between the MOS transistors 31 and 33 increases beyond the difference in threshold voltage between the two MO8 transistors, the voltage vE at the series connection point 35 increases.
But now it's smaller than before.

As this voltage vE becomes small, the resistance value of the MOS transistor 37 increases, which causes the voltage V
B is smaller than before. Then, if the on-resistance value of the MOS transistor 130 with this voltage VB as the dirt input is large, the increase in current in the resistor 2 will be
) This is offset by an increase in the on-resistance value of the transistor 13. That is, even if the channel length of the memory cell 11 is shortened, the current flowing through the resistor 21 is maintained at approximately the same value as before the length was shortened. In other words, the value of the write current flowing through the memory cell 1 is determined by the value of the write current flowing through the memory cell 1 when the phase change is 1+1M/7-1.

On the other hand, when the channel length of memory cell 1 becomes longer, the write 4H current in memory cell 1 decreases, contrary to the above, and the voltage A becomes larger than before the channel length becomes longer. Become. For this, control circuit L! Now, contrary to the above, the voltage vE becomes larger than before, and the output voltage vB also becomes larger than before. This is good, MO
The on-resistance value of the S transistor 13 becomes small, and the increase in the write current 'Lα applied to the memory cell 11 is canceled out. That is, even if the channel length of the memory cell 1 becomes longer, the value of the write current flowing through the memory cell J1 does not double before and after the channel length becomes longer, but remains almost constant.

Then, the value of the 1-input current of the memory cell 11 is determined by the resistance 2
It is determined by the value of the threshold voltage of the MOS transistors 31 and 33, and is not affected by variations in the channel length of the memory cell 11. In this way, the current flowing through the memory cell can be kept constant without being affected by the channel length of the memory cell.
It is not necessary to control the channel length of channel 1 to a depth < tl, thereby making it possible to widen the process margin.

FIG. 4 is a circuit diagram schematically showing the configuration of a data 1 input circuit portion of a nonvolatile semiconductor memory device according to another embodiment of the present invention. This embodiment differs from FIG. 3 in that a new control circuit LL is provided in place of the control circuit (2). This Wi! The I control circuit includes two depletion type MOS transistors 51 and 52 connected in series between the high voltage vP application point and the ground potential point. The dart of the other MOS transistor 52 is connected to the series connection point 22 from which the voltage VA is obtained, the dart of the other MOS transistor 52 is connected to the ground potential point, and the series connection point 53 of both MO8) runnostars 51 and 52 is connected to the series connection point 22 of the MO8 transistor 13. Connected to dart. Also, the above series connection point 5
The MO resistor 46, to which the inverted data D of the output data D from the input circuit 14 is inputted, is connected between the MO 3 and the ground potential point.

In a circuit having such a configuration, 1 and 1 of the memory cells 11
4. If the input current becomes smaller by % pressure v by d,
The resistance value of the MOS transistor 5 in the control circuit increases, and as a result, the voltage V at the υ series J connection point 53 becomes smaller than before. Then, MOS Tranogister 130
The on-resistance +Ii increases, and the heat sink current ηL of the memory cell 1 decreases. Next, contrary to the above, if the saved φ current in memory cell 1 decreases and the voltage vA increases, the resistance value of MOS transistor 5 decreases υ
As a result, the voltage V becomes larger than before, and the off-resistance value of the IVIO8 transistor 13 becomes smaller, so that the write current of the memory cell 11 increases. That is, in this embodiment as well, the write current can be kept almost constant without being affected by the channel length of the memory cell 1.

FIG. 5 is a circuit diagram schematically showing the configuration of a data loading circuit portion of a nonvolatile semiconductor memory device according to another embodiment of the present invention different from the forty-first embodiment. In this example circuit,
The resistor 2 is removed from the embodiment circuit of FIG. 3, and a control circuit (2) is provided in place of the control circuit (E). and the drain of the memory cell 11, that is, the series connection point 23 between the memory cell 11 and the column selection MOS transistor 12.
depletion type MO connected in series between
It is composed of S transistors 61 and 21 and enhancement type MOS transistors 62 and 6:j. And the above two MOS transistors 61 and 62
The series connection 64 is the Iv'l for the writing IfIJ.
The MO8) runnostar 46 is connected to the dirt of the O8 transistor 13, and is set to an off state by the inverted data D at the time of data reading, between this series connection point 64 and the ground potential point. ing.

In a circuit having such a configuration, when the memory cell 1 and the MOS transistor 12 are set to the on state by the decode outputs X and Y, the control circuit calculates the MOS transistor 61, 62
, 63, the current flows. Therefore, a voltage equal to the sum of the valley threshold values 'Ii of the MOS transistors 62 and 63 is applied between the drain of the memory cell 1 and the drain of the IOS transistor 13. By the way, Mos
Since the threshold voltage of the transistor is constant, even if the channel lengths of the memory cells vary, the voltage between the drain of the memory cell 11 and the drain of the MOS transistor 13 is kept almost constant. Therefore, the channel length of memory cell 1 is short9, and the flow J1. As the write current increases, the voltage at its drain decreases. However, memory cell 1
The potential difference between the drain of the MOS transistor 13 and the gate of the MOS transistor 13 is kept constant, and the increase in current is suppressed.
! On the other hand, contrary to the above, when the sink current decreases, the drain voltage of memory cell 1 increases.However, between the drain of memory cell 11 and the dirt of MOS transistor 13, Since the potential difference is kept constant, a decrease in the write current is suppressed. That is, in this embodiment as well, the write current of the memory cell 1 can be kept almost constant.

FIG. 6 is a circuit diagram showing a modification of the embodiment shown in FIG.

This modified example circuit differs from the one in FIG.
It is designed to be connected to the series connection point 19 of. Even with this configuration, the write current of the memory cell 11 can be kept almost constant, as in the case of FIG.

FIG. 7 is a circuit diagram schematically showing the configuration of a data write circuit portion of a nonvolatile semiconductor memory device according to still another embodiment of the present invention. In the embodiment circuit shown in FIG. 3, the series connection point 2 between the resistor 2 and the MOS transistor 13 is
MOS depending on the voltage vA at 2) transistor 13
The on-resistance value of this MOS transistor 13 is changed by controlling the gate 'ε pressure of the memory cell 1, thereby changing the on-resistance value of the MOS transistor 13.
In this embodiment, the write current of the memory cell 1 is made constant by changing the on-resistance value of the MOS l-transistor 12 for column selection. This is how it was done. That is, in this embodiment circuit, the MO for 4-input ILF control is
S) The output data D from the input circuit 14 shown in FIG.
Runno star 71 and column addresses Ao, Ao,...A
The output terminal of a column decoder L1 consisting of a decimal drive MOS transistor 72 with each n as a dirt input is connected to a read/write control side using a desolation/yon type MOS transistor 73 to which a voltage +t7/w is input to the gate. It is designed to connect via

Furthermore, a control circuit 76 consisting of an enhancement type MOS transistor 74 and a desolation type MOS transistor 75 connected in series is inserted between the high voltage VP application point and the dirt of the MOS (MOS) lannostar 12. The dart of the MOS transistor 74 is connected to the series connection point 22, and the MOS transistor 74 is connected to the series connection point 22.
5's dart is attached to the gate of MOS Tran Custa 12.

In a circuit having such a configuration, a high voltage vP is applied to the dirt of the MOS transistor 12 via the control circuit 76 only when the read/write control signal RIW is set to the "0" level and the column decoder 70 is established. Supplied. Here, the MOS l-Langistav 4 in the control circuit LA is
The dart is controlled by the voltage vA at the series connection point 22 of the resistor 21 and the MOS transistor 13. Therefore, the voltage of the decode output Y supplied to the MOS transistor 12 is set in such a direction that the write current flowing through the memory cell 1 is uniform, as in the case of the embodiment shown in FIG. '+1il) Nh'd so that the on-resistance value of the run raster 120 changes.

In this way, in each of the embodiments or modified examples shown in FIGS. 4 to 7, the write current can be kept almost constant without being affected by the channel length of the memory cell 11, so the process margin can be made wider than the gold. I can do it.

In addition, since the write current can be kept constant in the valley embodiment circuit described above, even if the channel length of the memory cell 1 is designed to be short, the data write time can be maintained without increasing the phase and write current. It is also possible to shorten the time.

Note that the resistor 2 in each of the embodiment circuits of FIGS. 3, 4, and 7 may be provided for each bit, but the resistor 2 may be provided for each bit. (MOS) may be provided only between the common connection point of the transistor.

〔Effect of the invention〕

As explained above, according to the present invention, depending on the value of the write current flowing through the memory cell, which one of the MOS transistor for indulgence control (MOS transistor for column selection and the MOS transistor for column selection) which serves as the load circuit of the memory cell is selected. Since one gate voltage is changed, a nearly constant sink current can flow regardless of the channel length of the memory cell, which makes it possible to widen the process margin. A semiconductor memory device can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional circuit, FIG. 2 is a curve diagram for explaining the circuit of FIG. 1, FIG. 3 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. Figure 5 is a circuit diagram showing the configuration of another embodiment of the present invention; Figure 6 is a circuit diagram showing the configuration of a modification of the circuit in Figure 5; The figure is a circuit diagram showing the configuration of another embodiment of the present invention. 1... Memory cell, 12... MOS transistor for column selection, 13... MOS transistor for write control, 14... Input circuit, 21... Resistor, 30° 50.60.76 ...Control circuit. Applicant's representative Patent attorney Takeshi Suzue Pork box 1 Figure 0 1o Figure 2 Figure 3 V2 4 Figure 4

Claims (4)

[Claims] (1) A memory cell that holds programmed data in a non-volatile manner, a variable impedance means inserted between the memory cell and a power source for data programming, and a control means that controls the variable impedance means. A nonvolatile semiconductor memory device characterized by: (2) The nonvolatile semiconductor memory device according to claim 1, wherein the variable impedance means is constituted by a gate-controlled MOS transistor. (3) The control means includes a fixed impedance element connected in series to the memory cell, and a control circuit that generates a voltage corresponding to a voltage at one end of the fixed impedance element and controls the variable impedance means with this voltage. A nonvolatile semiconductor memory device according to claim 1, comprising: (4) The t1iII control means is configured to generate a voltage according to the voltage at one end of the memory cell and control the variable impedance means with this voltage. non-volatile semiconductor memory device.