JPS5580154A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5580154A
JPS5580154A JP15543278A JP15543278A JPS5580154A JP S5580154 A JPS5580154 A JP S5580154A JP 15543278 A JP15543278 A JP 15543278A JP 15543278 A JP15543278 A JP 15543278A JP S5580154 A JPS5580154 A JP S5580154A
Authority
JP
Japan
Prior art keywords
stores
rom6
ram7
instruction
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15543278A
Other languages
Japanese (ja)
Inventor
Kyoichi Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15543278A priority Critical patent/JPS5580154A/en
Publication of JPS5580154A publication Critical patent/JPS5580154A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to change a program partially temporarily and confirm the operation of a control object device by executing the program of a readable memory in stead of a read-only memory by outputs of a comparator circuit for micro instruction addresses and a kip instruction generation circuit.
CONSTITUTION: Read-only memory ROM6 which is connected to maintenance control part 1 and stores micro instructions and readable read/write memory RAM7 which stores instructions to be stored in ROM6 are provided. This maintenance control part 1 is provided with address register 9 which stores addresses of ROM6, comparator circuit 12 which compares outputs of register 9 and address bus 5 with each other, and SRFF 15 which stores the output of AND gate 11. Further, address register 18 which stores addresses of RAM7 and skip instruction generation circuit 20 which generates a skip instruction by a skip code are provided, and an address of RAM7 is designated in stead of ROM6 by outputs of gate 11 and circuit 20, and execution of the instruction is executed by RAM7.
COPYRIGHT: (C)1980,JPO&Japio
JP15543278A 1978-12-13 1978-12-13 Microprogram control unit Pending JPS5580154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15543278A JPS5580154A (en) 1978-12-13 1978-12-13 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15543278A JPS5580154A (en) 1978-12-13 1978-12-13 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5580154A true JPS5580154A (en) 1980-06-17

Family

ID=15605883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15543278A Pending JPS5580154A (en) 1978-12-13 1978-12-13 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5580154A (en)

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