JPS5579533A - Counter - Google Patents

Counter

Info

Publication number
JPS5579533A
JPS5579533A JP15353678A JP15353678A JPS5579533A JP S5579533 A JPS5579533 A JP S5579533A JP 15353678 A JP15353678 A JP 15353678A JP 15353678 A JP15353678 A JP 15353678A JP S5579533 A JPS5579533 A JP S5579533A
Authority
JP
Japan
Prior art keywords
input
inverters
inverter
mos
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15353678A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Minoru Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15353678A priority Critical patent/JPS5579533A/en
Priority to US06/101,103 priority patent/US4356411A/en
Publication of JPS5579533A publication Critical patent/JPS5579533A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To remove factors impeding the high-speed operation, low power consumption and high integration of FF, and also to prevent racing from occurring by using several C-MOS inverters, supplied with clocks in common, as constituent elements of binary FF. CONSTITUTION:Binary FFs401 and 402 consist of master and slave FFs41 and 42, and 41' and 42' respectively. Then, 1st FF element 74 is formed connecting the input and output terminal of 1st C-MOS inverter 47 and that of 2nd inverter 52 provided to FF41 of this constitution, and a series circuit of p and n-type Trs53 and 54, and 55 and 56 is interposed between the output and input terminals of inverters 47 and 52, and 1st potential supply terminal. Further, 2nd FF element 67 where the input and output terminal of 3rd C-MOS inverter 61 formed in FF42 is connected to the input and output terminal of 4th C-MOS inverter 66 is formed and between output terminals of inverters 61 and 66, and 2nd potential supply terminal, n-type Trs57 and 58, and 62 and 63 connected.
JP15353678A 1978-12-12 1978-12-12 Counter Pending JPS5579533A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15353678A JPS5579533A (en) 1978-12-12 1978-12-12 Counter
US06/101,103 US4356411A (en) 1978-12-12 1979-12-07 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15353678A JPS5579533A (en) 1978-12-12 1978-12-12 Counter

Publications (1)

Publication Number Publication Date
JPS5579533A true JPS5579533A (en) 1980-06-16

Family

ID=15564653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15353678A Pending JPS5579533A (en) 1978-12-12 1978-12-12 Counter

Country Status (1)

Country Link
JP (1) JPS5579533A (en)

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