JPS5576423A - Electronic apparatus - Google Patents

Electronic apparatus

Info

Publication number
JPS5576423A
JPS5576423A JP15070978A JP15070978A JPS5576423A JP S5576423 A JPS5576423 A JP S5576423A JP 15070978 A JP15070978 A JP 15070978A JP 15070978 A JP15070978 A JP 15070978A JP S5576423 A JPS5576423 A JP S5576423A
Authority
JP
Japan
Prior art keywords
input
bfr2
key
time
bfr4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15070978A
Other languages
Japanese (ja)
Inventor
Minoru Machida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15070978A priority Critical patent/JPS5576423A/en
Publication of JPS5576423A publication Critical patent/JPS5576423A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)
  • Information Transfer Systems (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

PURPOSE: To decrease the input process exclusive time of the CPU at the key input time for the electronic desk computer by making the input buffer register (RFR) function as also the input/output BFR.
CONSTITUTION: The code of key 1 is received at input BFR2, and input buffer pointer 8 receives +8 every reception of the code at BFR2, and then the address is shown for the address of BFR2 to be taken in next at the key input time. Now if the switch control signal between input BFR2 and output BFR4 which is delivered from CPU3 indicates BFR4, AND gate 4 opens to send the contents of BFR4 to output device 5. At the same time, CPU3 detects the key input, and the control signal is sent so that device 5 is connected to BFR2 via control line 7. Thus AND gate 4A closes with gate 2A opened, and the contents of BFR2 is delivered to device 5. As a result, the exclusive time for the CPU's key the process of which is required with every key input can be decreased greatly.
COPYRIGHT: (C)1980,JPO&Japio
JP15070978A 1978-12-05 1978-12-05 Electronic apparatus Pending JPS5576423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15070978A JPS5576423A (en) 1978-12-05 1978-12-05 Electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15070978A JPS5576423A (en) 1978-12-05 1978-12-05 Electronic apparatus

Publications (1)

Publication Number Publication Date
JPS5576423A true JPS5576423A (en) 1980-06-09

Family

ID=15502685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15070978A Pending JPS5576423A (en) 1978-12-05 1978-12-05 Electronic apparatus

Country Status (1)

Country Link
JP (1) JPS5576423A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979731A (en) * 1972-12-08 1974-08-01
JPS50159638A (en) * 1974-06-12 1975-12-24

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979731A (en) * 1972-12-08 1974-08-01
JPS50159638A (en) * 1974-06-12 1975-12-24

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