JPS5569848A - Arithmetic controller - Google Patents

Arithmetic controller

Info

Publication number
JPS5569848A
JPS5569848A JP14313878A JP14313878A JPS5569848A JP S5569848 A JPS5569848 A JP S5569848A JP 14313878 A JP14313878 A JP 14313878A JP 14313878 A JP14313878 A JP 14313878A JP S5569848 A JPS5569848 A JP S5569848A
Authority
JP
Japan
Prior art keywords
bit
arithmetic
bit data
data
conversion part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14313878A
Other languages
Japanese (ja)
Inventor
Katsuyuki Shimokawa
Itaru Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14313878A priority Critical patent/JPS5569848A/en
Publication of JPS5569848A publication Critical patent/JPS5569848A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make multi-bit and single-bit arithmetic possible by combining a bit conversion part, which can extract one random bit from multi-bit data, with an arithmetic part which performs the arithmetic of multi-bit data.
CONSTITUTION: A controller consists of memory part 1 given addresses for respective blocks of sereval bits, arithmetic part 2 which processes multi-bit data, and input-output part 3 which transmits and receives data externally. Then, arithmetic part 2 is equipped with arithmetic logical operation unit 21 which process register files and multi-bit data, registers 23 and 24, bit conversion part 26, program counter 27, program status word part 28, etc. To process multi-bit data in the above-mentioned ocnstitution, data are made to by-pass conversion part 26 by a buffer built in conversion part 26 and for arithmetic of one-bit data, assigned bit data in memory part 1 are inputted to unit 21 and then stored in word part 28.
COPYRIGHT: (C)1980,JPO&Japio
JP14313878A 1978-11-20 1978-11-20 Arithmetic controller Pending JPS5569848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14313878A JPS5569848A (en) 1978-11-20 1978-11-20 Arithmetic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14313878A JPS5569848A (en) 1978-11-20 1978-11-20 Arithmetic controller

Publications (1)

Publication Number Publication Date
JPS5569848A true JPS5569848A (en) 1980-05-26

Family

ID=15331805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14313878A Pending JPS5569848A (en) 1978-11-20 1978-11-20 Arithmetic controller

Country Status (1)

Country Link
JP (1) JPS5569848A (en)

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