JPS5569848A - Arithmetic controller - Google Patents
Arithmetic controllerInfo
- Publication number
- JPS5569848A JPS5569848A JP14313878A JP14313878A JPS5569848A JP S5569848 A JPS5569848 A JP S5569848A JP 14313878 A JP14313878 A JP 14313878A JP 14313878 A JP14313878 A JP 14313878A JP S5569848 A JPS5569848 A JP S5569848A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- arithmetic
- bit data
- data
- conversion part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To make multi-bit and single-bit arithmetic possible by combining a bit conversion part, which can extract one random bit from multi-bit data, with an arithmetic part which performs the arithmetic of multi-bit data.
CONSTITUTION: A controller consists of memory part 1 given addresses for respective blocks of sereval bits, arithmetic part 2 which processes multi-bit data, and input-output part 3 which transmits and receives data externally. Then, arithmetic part 2 is equipped with arithmetic logical operation unit 21 which process register files and multi-bit data, registers 23 and 24, bit conversion part 26, program counter 27, program status word part 28, etc. To process multi-bit data in the above-mentioned ocnstitution, data are made to by-pass conversion part 26 by a buffer built in conversion part 26 and for arithmetic of one-bit data, assigned bit data in memory part 1 are inputted to unit 21 and then stored in word part 28.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14313878A JPS5569848A (en) | 1978-11-20 | 1978-11-20 | Arithmetic controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14313878A JPS5569848A (en) | 1978-11-20 | 1978-11-20 | Arithmetic controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5569848A true JPS5569848A (en) | 1980-05-26 |
Family
ID=15331805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14313878A Pending JPS5569848A (en) | 1978-11-20 | 1978-11-20 | Arithmetic controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5569848A (en) |
-
1978
- 1978-11-20 JP JP14313878A patent/JPS5569848A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5652454A (en) | Input/output control method of variable word length memory | |
JPS54117640A (en) | Memory address designation system | |
JPS5569848A (en) | Arithmetic controller | |
JPS5641574A (en) | Memory unit | |
JPS55105760A (en) | Memory control unit | |
JPS5776604A (en) | Numeric controller | |
JPS5759252A (en) | Operand control system of data flow computer | |
JPS5472646A (en) | High level language processing device | |
JPS6188334A (en) | Divider circuit | |
SU407312A1 (en) | PRIORITY DEVICE FOR PERFORMED | |
JPS5510626A (en) | General controller | |
JPS55105758A (en) | Parity check method and its unit | |
JPS55162163A (en) | Address extension system | |
JPS54141974A (en) | Sequence control unit | |
JPS5235530A (en) | Error correction system of memory | |
JPS5562576A (en) | Information processing unit with address conversion function | |
JPS553038A (en) | Microprogram control unit | |
JPS5543680A (en) | Address designation system | |
JPS5533228A (en) | Arithmetic unit | |
JPS5661096A (en) | Error detection system for read only memory electrically erasable | |
JPS54119831A (en) | Decoding circuit | |
JPS5567994A (en) | Data processor | |
JPS5533225A (en) | Arithmetic unit | |
JPS5563439A (en) | Instruction control system for direct data bit | |
EP0073004A3 (en) | Method for the operation of a cpu of a digital multibit computer system and the cpu for carrying out this method of operation |