JPS5567239A - Phase detector - Google Patents
Phase detectorInfo
- Publication number
- JPS5567239A JPS5567239A JP14077778A JP14077778A JPS5567239A JP S5567239 A JPS5567239 A JP S5567239A JP 14077778 A JP14077778 A JP 14077778A JP 14077778 A JP14077778 A JP 14077778A JP S5567239 A JPS5567239 A JP S5567239A
- Authority
- JP
- Japan
- Prior art keywords
- time
- mode
- detection
- ffs
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 abstract 5
- 230000002401 inhibitory effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To obtain a phase detector for PLL suitable for the control of a resonance tracking circuit system, etc., by inhibiting generation of signals of a phase error over 180 deg.. CONSTITUTION:Assuming that phases of input signals R and V have relations of (a) and (b), output (P7) of gate 9 resets FFs 6 and 7 to set an initial state in case of a L level, and therefore, (P7) is L and FFs 6 and 7 are reset during times t1- t2; and when input signal R becomes H-level at time t2, FF 6 is set to perform phase error detection of detection mode (mode 1) within 180 deg.. Even if FFs 6 and 7 are reset at time t4 by causes sucy as noise during operation and FF 7 is set at time t4+DELTAt to start the detection operation of detection mode (mode 2) over 180 deg., FF 7 is reset again at time t5-t6, so that detection of mode 1 can be performed by setting FF 6 again from time t6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53140777A JPS5851693B2 (en) | 1978-11-15 | 1978-11-15 | phase detector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53140777A JPS5851693B2 (en) | 1978-11-15 | 1978-11-15 | phase detector |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5567239A true JPS5567239A (en) | 1980-05-21 |
JPS5851693B2 JPS5851693B2 (en) | 1983-11-17 |
Family
ID=15276498
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53140777A Expired JPS5851693B2 (en) | 1978-11-15 | 1978-11-15 | phase detector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5851693B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0435618U (en) * | 1990-07-17 | 1992-03-25 |
-
1978
- 1978-11-15 JP JP53140777A patent/JPS5851693B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0435618U (en) * | 1990-07-17 | 1992-03-25 |
Also Published As
Publication number | Publication date |
---|---|
JPS5851693B2 (en) | 1983-11-17 |
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