JPS5452436A - Bit-phase synchronization system - Google Patents

Bit-phase synchronization system

Info

Publication number
JPS5452436A
JPS5452436A JP11865777A JP11865777A JPS5452436A JP S5452436 A JPS5452436 A JP S5452436A JP 11865777 A JP11865777 A JP 11865777A JP 11865777 A JP11865777 A JP 11865777A JP S5452436 A JPS5452436 A JP S5452436A
Authority
JP
Japan
Prior art keywords
circuit
phase
signal
digital signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11865777A
Other languages
Japanese (ja)
Inventor
Imio Fudemoto
Haruo Tsuda
Katsuya Okimi
Moriyuki Yamamoto
Susumu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP11865777A priority Critical patent/JPS5452436A/en
Publication of JPS5452436A publication Critical patent/JPS5452436A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To relieve manufacture conditions of a digital device by detecting the variation of a received digital signal, by detecting the phase difference between the output and a timing signal, and by selecting the results causing no error as to the discrimination of the input digital signal.
CONSTITUTION: Polyphase timing signal generating circuit 21 generates timing signals mutually different in phase such as S9 and S10 from reference timing signals from the same reference timing signal generating source. The variation of a received digital signal on the othe hand, is detected 12 and the phase difference between its output and signal S9 is detected by phase-difference detection circuit 14, thereby driving selector circuit 22. According to the output result of detection circuit 14, circuit 22 retimes the reception digital signal by using the timing signal, which has a phase causing no discrimination error of the input digital signal, selected by circuit 22. Consequently, the manufacture conditions of the digital device can be relieved
COPYRIGHT: (C)1979,JPO&Japio
JP11865777A 1977-10-04 1977-10-04 Bit-phase synchronization system Pending JPS5452436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11865777A JPS5452436A (en) 1977-10-04 1977-10-04 Bit-phase synchronization system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11865777A JPS5452436A (en) 1977-10-04 1977-10-04 Bit-phase synchronization system

Publications (1)

Publication Number Publication Date
JPS5452436A true JPS5452436A (en) 1979-04-25

Family

ID=14741982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11865777A Pending JPS5452436A (en) 1977-10-04 1977-10-04 Bit-phase synchronization system

Country Status (1)

Country Link
JP (1) JPS5452436A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03231533A (en) * 1990-02-06 1991-10-15 Fujitsu Ltd Data receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03231533A (en) * 1990-02-06 1991-10-15 Fujitsu Ltd Data receiver

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