JPS5553925A - Insulated gate field effect transistor logic circuit - Google Patents

Insulated gate field effect transistor logic circuit

Info

Publication number
JPS5553925A
JPS5553925A JP12700378A JP12700378A JPS5553925A JP S5553925 A JPS5553925 A JP S5553925A JP 12700378 A JP12700378 A JP 12700378A JP 12700378 A JP12700378 A JP 12700378A JP S5553925 A JPS5553925 A JP S5553925A
Authority
JP
Japan
Prior art keywords
field effect
effect transistor
logic circuit
transistor logic
insulated gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12700378A
Other languages
Japanese (ja)
Inventor
Hiroshi Osanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12700378A priority Critical patent/JPS5553925A/en
Publication of JPS5553925A publication Critical patent/JPS5553925A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To obtain an insulated gate field effect transistor logic circuit which can realize reduction of the current consumption by avoiding occurrence of the through- current flowing between the 1st and 2nd power sources. CONSTITUTION:Two units of P-channel MOSFET11 and 12 are connected in series between outout terminal 10 and power source VDD of one side. At the same time, two units of N-channel MOSFETs13 and 14 are connected in series between terminal 10 and power source VSS of the other side. The gate electrodes of FETs12 and 13 are connected in common, and input terminal 15 is led out from the joint between the both electrodes to supply input signal IN. Furthermore, clock signal phi1 is supplied to the gate electrode of FET11, and at the same time clock signal phi2 is supplied to the gate electrode of FET14 in such way that the active level period of phi2 may not overlap the active level period of phi1. In such way, the occurrence of the through-current flowing between the 1st and 2nd power sources can be avoided.
JP12700378A 1978-10-16 1978-10-16 Insulated gate field effect transistor logic circuit Pending JPS5553925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12700378A JPS5553925A (en) 1978-10-16 1978-10-16 Insulated gate field effect transistor logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12700378A JPS5553925A (en) 1978-10-16 1978-10-16 Insulated gate field effect transistor logic circuit

Publications (1)

Publication Number Publication Date
JPS5553925A true JPS5553925A (en) 1980-04-19

Family

ID=14949265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12700378A Pending JPS5553925A (en) 1978-10-16 1978-10-16 Insulated gate field effect transistor logic circuit

Country Status (1)

Country Link
JP (1) JPS5553925A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198920A (en) * 1984-03-22 1985-10-08 Nec Ic Microcomput Syst Ltd Interface circuit
WO2009034749A1 (en) * 2007-09-12 2009-03-19 Sharp Kabushiki Kaisha Shift register
US8269714B2 (en) 2007-09-12 2012-09-18 Sharp Kabushiki Kaisha Shift register

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115941A (en) * 1974-07-31 1976-02-07 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115941A (en) * 1974-07-31 1976-02-07 Hitachi Ltd

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198920A (en) * 1984-03-22 1985-10-08 Nec Ic Microcomput Syst Ltd Interface circuit
WO2009034749A1 (en) * 2007-09-12 2009-03-19 Sharp Kabushiki Kaisha Shift register
US8269714B2 (en) 2007-09-12 2012-09-18 Sharp Kabushiki Kaisha Shift register
US8269713B2 (en) 2007-09-12 2012-09-18 Sharp Kabushiki Kaisha Shift register
US8493312B2 (en) 2007-09-12 2013-07-23 Sharp Kabushiki Kaisha Shift register

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