JPS5553770A - Electronic cash register - Google Patents

Electronic cash register

Info

Publication number
JPS5553770A
JPS5553770A JP12755878A JP12755878A JPS5553770A JP S5553770 A JPS5553770 A JP S5553770A JP 12755878 A JP12755878 A JP 12755878A JP 12755878 A JP12755878 A JP 12755878A JP S5553770 A JPS5553770 A JP S5553770A
Authority
JP
Japan
Prior art keywords
cpu4
adjustment
case
pack
data pack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12755878A
Other languages
Japanese (ja)
Inventor
Minoru Deguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba TEC Corp
Original Assignee
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Co Ltd filed Critical Tokyo Electric Co Ltd
Priority to JP12755878A priority Critical patent/JPS5553770A/en
Publication of JPS5553770A publication Critical patent/JPS5553770A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To cause no inconvenience for the adjustment work even in case the adjustment is carried out with no connection to the data pack mistakenly by holding the memory with no connection to the data pack in the case of the specifications to use the data pack.
CONSTITUTION: In case the contents of option board 10 indicates existence of the date pack, CPU4 conveys the control code to data pack 12 via transmission control circuit 11 for holding for a fixed time. If some answer is given from pack 12 within that period, CPU4 gives the address conversion for the program selection to ROM6 and then stops the transmission in case no answer is given. And the designation signal is transmitted to ROM6 from CPU4 in order to select the routine for presentation of the adjustment report. Thus the contents of RAM5 is not cleared by the rewriting signal sent from CPU4 but held to display 8 HOLD via display driving circuit 7. As a result, no inconvenience is caused for the adjustment work by holding the contents of the memory even though the adjustment is carried out with no connection to the data pack 12 mistakenly.
COPYRIGHT: (C)1980,JPO&Japio
JP12755878A 1978-10-17 1978-10-17 Electronic cash register Pending JPS5553770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12755878A JPS5553770A (en) 1978-10-17 1978-10-17 Electronic cash register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12755878A JPS5553770A (en) 1978-10-17 1978-10-17 Electronic cash register

Publications (1)

Publication Number Publication Date
JPS5553770A true JPS5553770A (en) 1980-04-19

Family

ID=14962982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12755878A Pending JPS5553770A (en) 1978-10-17 1978-10-17 Electronic cash register

Country Status (1)

Country Link
JP (1) JPS5553770A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5962974A (en) * 1982-09-30 1984-04-10 Omron Tateisi Electronics Co Electronic cash register

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5962974A (en) * 1982-09-30 1984-04-10 Omron Tateisi Electronics Co Electronic cash register

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