JPS5544980A - Trigger point display device - Google Patents

Trigger point display device

Info

Publication number
JPS5544980A
JPS5544980A JP11957878A JP11957878A JPS5544980A JP S5544980 A JPS5544980 A JP S5544980A JP 11957878 A JP11957878 A JP 11957878A JP 11957878 A JP11957878 A JP 11957878A JP S5544980 A JPS5544980 A JP S5544980A
Authority
JP
Japan
Prior art keywords
counter
signals
trigger point
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11957878A
Other languages
Japanese (ja)
Inventor
Hideo Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11957878A priority Critical patent/JPS5544980A/en
Publication of JPS5544980A publication Critical patent/JPS5544980A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To facilitate the handling by automatically calculating the trigger point from a delay number and the storage capacity of a memory unit.
CONSTITUTION: In response to the signals from an input terminal 42, a circuit is reset under an initial condition. When load signals are generated, a delay counter 28 and a counter 29 is loaded with the complementary number of the delay number, and a down counter 30 is loaded with the memory capacity number. When the signals to be fed to the input terminal 42 are terminated, a memory 21 starts its memory operation. At the same time, the counter 29 is counted up to generate the signals which will gate the down-counter 30. The coincidence signals generated by a coincidence circuit 32 are fed as a brightness modulating signal to a Z axis circuit 34 thereby to display the position of the trigger point.
COPYRIGHT: (C)1980,JPO&Japio
JP11957878A 1978-09-27 1978-09-27 Trigger point display device Pending JPS5544980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11957878A JPS5544980A (en) 1978-09-27 1978-09-27 Trigger point display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11957878A JPS5544980A (en) 1978-09-27 1978-09-27 Trigger point display device

Publications (1)

Publication Number Publication Date
JPS5544980A true JPS5544980A (en) 1980-03-29

Family

ID=14764809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11957878A Pending JPS5544980A (en) 1978-09-27 1978-09-27 Trigger point display device

Country Status (1)

Country Link
JP (1) JPS5544980A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5181666A (en) * 1975-01-14 1976-07-17 Iwatsu Electric Co Ltd SHINGOKANSOKUSOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5181666A (en) * 1975-01-14 1976-07-17 Iwatsu Electric Co Ltd SHINGOKANSOKUSOCHI

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