JPS5544755A - Semiconductor container - Google Patents

Semiconductor container

Info

Publication number
JPS5544755A
JPS5544755A JP11822378A JP11822378A JPS5544755A JP S5544755 A JPS5544755 A JP S5544755A JP 11822378 A JP11822378 A JP 11822378A JP 11822378 A JP11822378 A JP 11822378A JP S5544755 A JPS5544755 A JP S5544755A
Authority
JP
Japan
Prior art keywords
dielectric
stem
uni
projection
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11822378A
Other languages
Japanese (ja)
Inventor
Isamu Nagameguri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11822378A priority Critical patent/JPS5544755A/en
Publication of JPS5544755A publication Critical patent/JPS5544755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Abstract

PURPOSE: To economically obtain a uni-power-source bias system by covering the surface of a conductor fixed to a semiconductor element and to be connected to the external circuit with a dielectric usable as a bypass condenser.
CONSTITUTION: A conductive stem J has a projection. An FFT chip I is fixed to the projection, and a dielectric is bonded to the other surface of the conductive stem J. A surface-metallized insulator K is provided around the stem J, the electrode of the chip I and the metallized layer of the insulator K are interconnected by thin metallic wires, drain and gate electrodes A and B are attached thereto. A dielectric G is provided by bonding a dielecric such as teflon or metal such as Al which is changed into dielectric by forming with chemically treating. The surface, on which the dielectric G is bonded, is directly to an earthing conductor. Thereby, a uni- power-source bias system can be realized at a low cost.
COPYRIGHT: (C)1980,JPO&Japio
JP11822378A 1978-09-25 1978-09-25 Semiconductor container Pending JPS5544755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11822378A JPS5544755A (en) 1978-09-25 1978-09-25 Semiconductor container

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11822378A JPS5544755A (en) 1978-09-25 1978-09-25 Semiconductor container

Publications (1)

Publication Number Publication Date
JPS5544755A true JPS5544755A (en) 1980-03-29

Family

ID=14731261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11822378A Pending JPS5544755A (en) 1978-09-25 1978-09-25 Semiconductor container

Country Status (1)

Country Link
JP (1) JPS5544755A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825282A (en) * 1985-01-30 1989-04-25 Fujitsu Limited Semiconductor package having side walls, earth-bonding terminal, and earth lead formed in a unitary structure
JPH03167866A (en) * 1989-11-28 1991-07-19 Fujitsu Ltd Mounting structure of ic chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825282A (en) * 1985-01-30 1989-04-25 Fujitsu Limited Semiconductor package having side walls, earth-bonding terminal, and earth lead formed in a unitary structure
JPH03167866A (en) * 1989-11-28 1991-07-19 Fujitsu Ltd Mounting structure of ic chip

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