JPS5544637A - Display device - Google Patents

Display device

Info

Publication number
JPS5544637A
JPS5544637A JP11786478A JP11786478A JPS5544637A JP S5544637 A JPS5544637 A JP S5544637A JP 11786478 A JP11786478 A JP 11786478A JP 11786478 A JP11786478 A JP 11786478A JP S5544637 A JPS5544637 A JP S5544637A
Authority
JP
Japan
Prior art keywords
copying
circuit
area
viewer
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11786478A
Other languages
Japanese (ja)
Other versions
JPS5827510B2 (en
Inventor
Kenji Masai
Yoshi Ozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53117864A priority Critical patent/JPS5827510B2/en
Publication of JPS5544637A publication Critical patent/JPS5544637A/en
Publication of JPS5827510B2 publication Critical patent/JPS5827510B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To realize the copying of the pattern displayed at part on the viewer to another area on the viewer by securing a processable constitution independently for the copying function.
CONSTITUTION: Copying control circuit 40 receives vertical and horizontal address data Vi and Hi to produce new addresses Vi' and Hi' each. Among the process functions of circuit 40 to perform the address conversion, the address designation of the copying destination is carried out via address bus AB and data buss DB. Bus AB performs the register designation within circuit 40, and bus DB performs designation for the data to be set to the designated register. To secure the square area for the copying destination, two registers are used for the upper left start point and the right lower finish point of the area. Thus the vertical and horizontal addresses of refresh memory 34 are converted temporarily in circuit 40, and the vertical and horizontal addresses on the viewer plus that of the refresh memory are defined as copying destination area 22 each to obtain the display state as shown in Fig. b.
COPYRIGHT: (C)1980,JPO&Japio
JP53117864A 1978-09-27 1978-09-27 Display control method Expired JPS5827510B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53117864A JPS5827510B2 (en) 1978-09-27 1978-09-27 Display control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53117864A JPS5827510B2 (en) 1978-09-27 1978-09-27 Display control method

Publications (2)

Publication Number Publication Date
JPS5544637A true JPS5544637A (en) 1980-03-29
JPS5827510B2 JPS5827510B2 (en) 1983-06-09

Family

ID=14722176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53117864A Expired JPS5827510B2 (en) 1978-09-27 1978-09-27 Display control method

Country Status (1)

Country Link
JP (1) JPS5827510B2 (en)

Also Published As

Publication number Publication date
JPS5827510B2 (en) 1983-06-09

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