JPS5537655A - Control system of input-output device - Google Patents

Control system of input-output device

Info

Publication number
JPS5537655A
JPS5537655A JP11050778A JP11050778A JPS5537655A JP S5537655 A JPS5537655 A JP S5537655A JP 11050778 A JP11050778 A JP 11050778A JP 11050778 A JP11050778 A JP 11050778A JP S5537655 A JPS5537655 A JP S5537655A
Authority
JP
Japan
Prior art keywords
input
address
end state
state information
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11050778A
Other languages
Japanese (ja)
Inventor
Minekazu Maruoka
Ryushi Hiroya
Toshio Katsuki
Makoto Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11050778A priority Critical patent/JPS5537655A/en
Publication of JPS5537655A publication Critical patent/JPS5537655A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make branch control possible not by an instruction but by command chaining even when an input-output device sending end state information of different format is installed in one channel controller.
CONSTITUTION: After input-output device IO0 ends prescribed opereration, information stored in an address of private main memory unit MM of device IO0 is read out. On receiving operation end state information from device IO0, input-output controller IOC0 makes a check on a branch bit; when branch operation is not required, the address information is written as it is and when it is required, a branch-destination address is added to the address information by adder circuit ADX and then written to the exclusive-use address for IO0 of memory unit MM. From unit IOC0 to channel controller CHC, interruption request R is sent together with operation end state information I of IO0. Consequently, IOs differing in the pattern of the operation end state information can be mixed and installed in one CHC device, so that flexibility of CHC will increase.
COPYRIGHT: (C)1980,JPO&Japio
JP11050778A 1978-09-08 1978-09-08 Control system of input-output device Pending JPS5537655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11050778A JPS5537655A (en) 1978-09-08 1978-09-08 Control system of input-output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11050778A JPS5537655A (en) 1978-09-08 1978-09-08 Control system of input-output device

Publications (1)

Publication Number Publication Date
JPS5537655A true JPS5537655A (en) 1980-03-15

Family

ID=14537520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11050778A Pending JPS5537655A (en) 1978-09-08 1978-09-08 Control system of input-output device

Country Status (1)

Country Link
JP (1) JPS5537655A (en)

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