JPS5487452A - Cross-call interruption control system - Google Patents

Cross-call interruption control system

Info

Publication number
JPS5487452A
JPS5487452A JP15593277A JP15593277A JPS5487452A JP S5487452 A JPS5487452 A JP S5487452A JP 15593277 A JP15593277 A JP 15593277A JP 15593277 A JP15593277 A JP 15593277A JP S5487452 A JPS5487452 A JP S5487452A
Authority
JP
Japan
Prior art keywords
devices
cross
call
interruption
controllers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15593277A
Other languages
Japanese (ja)
Inventor
Kazeo Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15593277A priority Critical patent/JPS5487452A/en
Publication of JPS5487452A publication Critical patent/JPS5487452A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to send a report on the interruption factor of a device to a higher unit in any other system when a partition system is constituted by using an adaptor enabling a dynamic cross-call.
CONSTITUTION: The system allowing CPUs #1 and #2 to attain access to cascaded devices #0 and #7 by being provided with cross-call adaptor ADP making dynamic calls to devices #0 to #7 and device controllers #1 and #2 is equipped with decoder DEC decoding device assignment bits DVSL1 to DVSL4 from controllers #0 and #1 and short circuit STR which corresponds to devices #0 to #7. Further, this circuit STR is provided onto the control line which sends out an interruption from controller #1 and #2 to interruption registers IntRegA or IntRegB, and circuit STR is so set that devices #0 to #3 for dynamic cross-call control will be shorted with partition-connection devices #4 to #7 opened.
COPYRIGHT: (C)1979,JPO&Japio
JP15593277A 1977-12-23 1977-12-23 Cross-call interruption control system Pending JPS5487452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15593277A JPS5487452A (en) 1977-12-23 1977-12-23 Cross-call interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15593277A JPS5487452A (en) 1977-12-23 1977-12-23 Cross-call interruption control system

Publications (1)

Publication Number Publication Date
JPS5487452A true JPS5487452A (en) 1979-07-11

Family

ID=15616654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15593277A Pending JPS5487452A (en) 1977-12-23 1977-12-23 Cross-call interruption control system

Country Status (1)

Country Link
JP (1) JPS5487452A (en)

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