JPS5533306A - Supervisory system for eye pattern - Google Patents

Supervisory system for eye pattern

Info

Publication number
JPS5533306A
JPS5533306A JP10482478A JP10482478A JPS5533306A JP S5533306 A JPS5533306 A JP S5533306A JP 10482478 A JP10482478 A JP 10482478A JP 10482478 A JP10482478 A JP 10482478A JP S5533306 A JPS5533306 A JP S5533306A
Authority
JP
Japan
Prior art keywords
circuit
output
eye pattern
comparator
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10482478A
Other languages
Japanese (ja)
Other versions
JPS5814111B2 (en
Inventor
Takeo Sato
Mitsuhiro Matsue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10482478A priority Critical patent/JPS5814111B2/en
Publication of JPS5533306A publication Critical patent/JPS5533306A/en
Publication of JPS5814111B2 publication Critical patent/JPS5814111B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits

Abstract

PURPOSE:To realize the accurate supervisory for the circuit with the excellent linearity and without any effect of the circuit disturbance by applying both the phase lock loop and the multiplier. CONSTITUTION:The FSK input signal is amplified 21 and limited 22, and the output is supplied to phase lock loop PLL circuit consisting of phase comparator 23 and phase control oscillator 24. And the output of the PLL circuir is turned to the demodulation output by comparator 26 and via LPF25. The sampling supervisory system comprises limiter 27, multiplier 28 and LPF29, and the output of limiter 27 and oscillator 24 are multiplied 28 together and then filtered 29 to obtain the eye pattern. The eye pattern is then applied to sample holding circuit 31; while the output of sampling circuit 30 which gives sampling to the output of comparator 26 gives the sample holding to the eye pattern at circuit 31 and then supplies the eye pattern to supervisory circuit 32.
JP10482478A 1978-08-30 1978-08-30 Eye pattern monitoring method Expired JPS5814111B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10482478A JPS5814111B2 (en) 1978-08-30 1978-08-30 Eye pattern monitoring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10482478A JPS5814111B2 (en) 1978-08-30 1978-08-30 Eye pattern monitoring method

Publications (2)

Publication Number Publication Date
JPS5533306A true JPS5533306A (en) 1980-03-08
JPS5814111B2 JPS5814111B2 (en) 1983-03-17

Family

ID=14391136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10482478A Expired JPS5814111B2 (en) 1978-08-30 1978-08-30 Eye pattern monitoring method

Country Status (1)

Country Link
JP (1) JPS5814111B2 (en)

Also Published As

Publication number Publication date
JPS5814111B2 (en) 1983-03-17

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