JPS5533009A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5533009A
JPS5533009A JP10437478A JP10437478A JPS5533009A JP S5533009 A JPS5533009 A JP S5533009A JP 10437478 A JP10437478 A JP 10437478A JP 10437478 A JP10437478 A JP 10437478A JP S5533009 A JPS5533009 A JP S5533009A
Authority
JP
Japan
Prior art keywords
type
region
vertical transistor
gate
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10437478A
Other languages
Japanese (ja)
Inventor
Koichi Kanzaki
Akihiko Furukawa
Hajime Sasaki
Minoru Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10437478A priority Critical patent/JPS5533009A/en
Priority to GB7929601A priority patent/GB2029102B/en
Publication of JPS5533009A publication Critical patent/JPS5533009A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]
    • H01L27/0244I2L structures integrated in combination with analog structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To provide a multifunctional IC through coexistence of a normal vertical transistor having a given emitter-to-collector voltage resistance and I2L greater in the maximum action speed.
CONSTITUTION: Two N+ type buried regions 2 are formed by diffusion on a P type Si substrate 1 and a N type layer 3 is epitaxially grown on the entire regions. Then, the layer 3 is separated into two islands by a P+ type region 4, and an I2L gate is provided on one island and a vertical transistor for linear circuit on the other island. Here, the I2L gate is formed as a double base construction having a P type external base region 6 greater in the degree of diffusion from the surface and a P type internal base shallower than the region 6 immediately below the collector 9. On the other hand, the region is made common for the base of the vertical transistor while a N+ type region 9 is provided in common use for the collector of the vertical transistor and the emitter of the linear transistor in the I2L gate. Thereafter, electrodes are mounted in the respective regions. In this manner, the operational frequency of I2L thus coexiting can be improced.
COPYRIGHT: (C)1980,JPO&Japio
JP10437478A 1978-08-29 1978-08-29 Semiconductor integrated circuit Pending JPS5533009A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10437478A JPS5533009A (en) 1978-08-29 1978-08-29 Semiconductor integrated circuit
GB7929601A GB2029102B (en) 1978-08-29 1979-08-24 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10437478A JPS5533009A (en) 1978-08-29 1978-08-29 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5533009A true JPS5533009A (en) 1980-03-08

Family

ID=14379004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10437478A Pending JPS5533009A (en) 1978-08-29 1978-08-29 Semiconductor integrated circuit

Country Status (2)

Country Link
JP (1) JPS5533009A (en)
GB (1) GB2029102B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5261977A (en) * 1975-11-18 1977-05-21 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its production
JPS54160187A (en) * 1978-06-08 1979-12-18 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5261977A (en) * 1975-11-18 1977-05-21 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its production
JPS54160187A (en) * 1978-06-08 1979-12-18 Matsushita Electric Ind Co Ltd Semiconductor device

Also Published As

Publication number Publication date
GB2029102B (en) 1983-05-05
GB2029102A (en) 1980-03-12

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