JPS5530782A - Execution control system of instruction - Google Patents

Execution control system of instruction

Info

Publication number
JPS5530782A
JPS5530782A JP10382578A JP10382578A JPS5530782A JP S5530782 A JPS5530782 A JP S5530782A JP 10382578 A JP10382578 A JP 10382578A JP 10382578 A JP10382578 A JP 10382578A JP S5530782 A JPS5530782 A JP S5530782A
Authority
JP
Japan
Prior art keywords
operand
write
execution
data
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10382578A
Other languages
Japanese (ja)
Other versions
JPS5646614B2 (en
Inventor
Kiyoshi Yada
Shigeo Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10382578A priority Critical patent/JPS5530782A/en
Publication of JPS5530782A publication Critical patent/JPS5530782A/en
Publication of JPS5646614B2 publication Critical patent/JPS5646614B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To enable to reduce the time required for execution, by providing a simple operation circuit in readout and write-in control section of the main memory unit.
CONSTITUTION: A given operation 9 is made between the second operand of one byte length of the readout register WD and the first operand at the write-in register RD, and the result is incorporated with the data in remaining 7-byte except the first operand in the data of RD2 in the merge circuit 4 and it is written in the main memory unit MS. That is, taking the store cycle as ST, the access time Ta required for the set of the data of one word including the first operand to RD2 through access to MS and the operation between the circuit 9 and CPU are parallelly made, then the operation of execution is finished (b) by the set of the condition code due to the result of operation with the operation 9 and the write-in cycle time Twc required for the write-in to MS, to reduce the execution time than conventional system (a).
COPYRIGHT: (C)1980,JPO&Japio
JP10382578A 1978-08-28 1978-08-28 Execution control system of instruction Granted JPS5530782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10382578A JPS5530782A (en) 1978-08-28 1978-08-28 Execution control system of instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10382578A JPS5530782A (en) 1978-08-28 1978-08-28 Execution control system of instruction

Publications (2)

Publication Number Publication Date
JPS5530782A true JPS5530782A (en) 1980-03-04
JPS5646614B2 JPS5646614B2 (en) 1981-11-04

Family

ID=14364180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10382578A Granted JPS5530782A (en) 1978-08-28 1978-08-28 Execution control system of instruction

Country Status (1)

Country Link
JP (1) JPS5530782A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143323A (en) * 1991-01-30 1993-06-11 Internatl Business Mach Corp <Ibm> Method and apparatus for executing type-1 diadic instruction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143323A (en) * 1991-01-30 1993-06-11 Internatl Business Mach Corp <Ibm> Method and apparatus for executing type-1 diadic instruction

Also Published As

Publication number Publication date
JPS5646614B2 (en) 1981-11-04

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