JPS5530707A - Direct memory access control unit - Google Patents
Direct memory access control unitInfo
- Publication number
- JPS5530707A JPS5530707A JP10182478A JP10182478A JPS5530707A JP S5530707 A JPS5530707 A JP S5530707A JP 10182478 A JP10182478 A JP 10182478A JP 10182478 A JP10182478 A JP 10182478A JP S5530707 A JPS5530707 A JP S5530707A
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- memorized
- control unit
- fifo19
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bus Control (AREA)
Abstract
PURPOSE: To shorten the processing time by installing the first-in/first-out register FIFO to direct memory access DMA control unit and giving an access to the main memory based on the address set up at register FIFO.
CONSTITUTION: DMA control unit 3 is installed between input/output bus 100 and device control circuit 200. Head address data EA1WEAm are memorized in FIFO19 of unit 3 prior to the data draw-in and with every channel CH sent from CPU via line 21. The input is carried out in the order of the CH, and the CH-based data is set up in the continuous address. As a result, the head address of each CH features the discontinuous value. With start of the data draw-in, EA1 of FIFO19 is read out. And data 1.1 of the address is memorized in EA1 of the main memory. This data is also given +1 via Add-1 circuit 20 to be memorized into the address in which EAm of FIFO19 is set up and in the form of data EA1+1. In such process, the data is memorized in CH2... and the main memory, thus omitting the data editing process.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53101824A JPS5953565B2 (en) | 1978-08-23 | 1978-08-23 | Direct memory access control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53101824A JPS5953565B2 (en) | 1978-08-23 | 1978-08-23 | Direct memory access control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5530707A true JPS5530707A (en) | 1980-03-04 |
JPS5953565B2 JPS5953565B2 (en) | 1984-12-26 |
Family
ID=14310852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53101824A Expired JPS5953565B2 (en) | 1978-08-23 | 1978-08-23 | Direct memory access control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5953565B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60168256A (en) * | 1984-02-10 | 1985-08-31 | Hitachi Ltd | Address management system of various direct memory access |
JPS60181862A (en) * | 1984-02-29 | 1985-09-17 | Hitachi Ltd | Setting system of dma transfer buffer |
JPS60183666A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
JPS60183665A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
-
1978
- 1978-08-23 JP JP53101824A patent/JPS5953565B2/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60168256A (en) * | 1984-02-10 | 1985-08-31 | Hitachi Ltd | Address management system of various direct memory access |
JPS60181862A (en) * | 1984-02-29 | 1985-09-17 | Hitachi Ltd | Setting system of dma transfer buffer |
JPS60183666A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
JPS60183665A (en) * | 1984-03-02 | 1985-09-19 | Hitachi Ltd | Dma transfer control system |
JPH0565896B2 (en) * | 1984-03-02 | 1993-09-20 | Hitachi Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS5953565B2 (en) | 1984-12-26 |
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