JPS553040A - Comparator circuit - Google Patents

Comparator circuit

Info

Publication number
JPS553040A
JPS553040A JP7502678A JP7502678A JPS553040A JP S553040 A JPS553040 A JP S553040A JP 7502678 A JP7502678 A JP 7502678A JP 7502678 A JP7502678 A JP 7502678A JP S553040 A JPS553040 A JP S553040A
Authority
JP
Japan
Prior art keywords
logic
flop
given
terminal
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7502678A
Other languages
Japanese (ja)
Inventor
Kazuo Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7502678A priority Critical patent/JPS553040A/en
Publication of JPS553040A publication Critical patent/JPS553040A/en
Pending legal-status Critical Current

Links

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  • Tests Of Electronic Circuits (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To facilitate the automatic cut-off and the diagnosis when the disagreement is detected by providing the flip-flop within the comparator circuit. CONSTITUTION:At the normal time, the plural tested signals under the same logic state are applied to exclusive logic sum circuits 20-25 via input terminals 0-3. If the abnormal tested signal is given to input terminal 3, exclusive logic sum circuits 22, 24 and 25 connected to terminal 3 become logic ''1'' with other logic sum circuits truned to ''0''. Accordingly, only the output of logic product circuit 49 becomes logic ''1'', and other logic product circuits 46-48 feature ''0''. As a result, only flop-flop FF53 becomes ''1'' with FF50-52 turning to ''0'', and these logic value are given to diagnosis device 100 via output terminals 90-93. And the output of FF53 is given to AND circuit 73 to make ineffective the signals sent from terminal 3.
JP7502678A 1978-06-20 1978-06-20 Comparator circuit Pending JPS553040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7502678A JPS553040A (en) 1978-06-20 1978-06-20 Comparator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7502678A JPS553040A (en) 1978-06-20 1978-06-20 Comparator circuit

Publications (1)

Publication Number Publication Date
JPS553040A true JPS553040A (en) 1980-01-10

Family

ID=13564248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7502678A Pending JPS553040A (en) 1978-06-20 1978-06-20 Comparator circuit

Country Status (1)

Country Link
JP (1) JPS553040A (en)

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