JPS553036A - Data processor - Google Patents

Data processor

Info

Publication number
JPS553036A
JPS553036A JP7502078A JP7502078A JPS553036A JP S553036 A JPS553036 A JP S553036A JP 7502078 A JP7502078 A JP 7502078A JP 7502078 A JP7502078 A JP 7502078A JP S553036 A JPS553036 A JP S553036A
Authority
JP
Japan
Prior art keywords
output
order
counter
branch
confirmation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7502078A
Other languages
Japanese (ja)
Inventor
Takanori Umeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7502078A priority Critical patent/JPS553036A/en
Publication of JPS553036A publication Critical patent/JPS553036A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To ensure the confirmation for not only the program error but for the interruption process situation by providing the program counter, the memory means and the output means to the processor and then reading out the contents of the counter when necessary.
CONSTITUTION: The contents of program counter 2 is delivered from counter 2 while the logic product is secured at AND gate 3 by the output of order decoder 1, and then memorized in exclusive memory device 4. Then the output from device 4 is supplied to output device 6 via output control circuit 5. Now, if the prescribed branch order plus the order to be executed next are decided, the output is produced at decoder 1 at the execution time of the branch order and the execution time of one order immediately after the branching. As a result, the address of the branch order plus the address of the order executed after the branch order are written into device 4 from counter 2 via gate 3, and the output is produced at device 6 in accordance with the output request given from circuit 5 for the confirmation.
COPYRIGHT: (C)1980,JPO&Japio
JP7502078A 1978-06-20 1978-06-20 Data processor Pending JPS553036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7502078A JPS553036A (en) 1978-06-20 1978-06-20 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7502078A JPS553036A (en) 1978-06-20 1978-06-20 Data processor

Publications (1)

Publication Number Publication Date
JPS553036A true JPS553036A (en) 1980-01-10

Family

ID=13564067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7502078A Pending JPS553036A (en) 1978-06-20 1978-06-20 Data processor

Country Status (1)

Country Link
JP (1) JPS553036A (en)

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