JPS5518122A - Test system for subscriber circuit - Google Patents

Test system for subscriber circuit

Info

Publication number
JPS5518122A
JPS5518122A JP9053578A JP9053578A JPS5518122A JP S5518122 A JPS5518122 A JP S5518122A JP 9053578 A JP9053578 A JP 9053578A JP 9053578 A JP9053578 A JP 9053578A JP S5518122 A JPS5518122 A JP S5518122A
Authority
JP
Japan
Prior art keywords
test
faulty
tester
result
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9053578A
Other languages
Japanese (ja)
Inventor
Kiyoshi Takeuchi
Yosoji Hirayanagi
Tadashi Kawazoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9053578A priority Critical patent/JPS5518122A/en
Publication of JPS5518122A publication Critical patent/JPS5518122A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
    • H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
    • H04M3/30—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for subscriber's lines, for the local loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To save the trouble for the retrial from the tester to the test board in case the test result is faulty in the subscriber circuit test, by securing an automatic announcement for the faulty test result and at the same time giving a connection to the test board. CONSTITUTION:The tester calls out the circuit test unit from the subscriber telephone set to be tested via dial 114, thus enabling the test for the subscriber circuit. The test result is announced immediately in voice. In case the test result is faulty, the announcement is given for the faulty result. At the same time, the timing relay circuit operates to close the contact nearly at the time the anneouncement is over and then to give a connection to the test board where the test operator is. The test operator talks to the tester to carry out subsequently the necessary circuit test. Also the test can be discontinued if the tester puts the telephone receiver at the announcement time of the faulty test result.
JP9053578A 1978-07-26 1978-07-26 Test system for subscriber circuit Pending JPS5518122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9053578A JPS5518122A (en) 1978-07-26 1978-07-26 Test system for subscriber circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9053578A JPS5518122A (en) 1978-07-26 1978-07-26 Test system for subscriber circuit

Publications (1)

Publication Number Publication Date
JPS5518122A true JPS5518122A (en) 1980-02-08

Family

ID=14001096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9053578A Pending JPS5518122A (en) 1978-07-26 1978-07-26 Test system for subscriber circuit

Country Status (1)

Country Link
JP (1) JPS5518122A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59141861A (en) * 1983-02-01 1984-08-14 Nec Corp Test system for subscriber line

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59141861A (en) * 1983-02-01 1984-08-14 Nec Corp Test system for subscriber line
JPH0317266B2 (en) * 1983-02-01 1991-03-07 Nippon Electric Co

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