JPS55161426A - Malfunction detecting unit - Google Patents

Malfunction detecting unit

Info

Publication number
JPS55161426A
JPS55161426A JP7090279A JP7090279A JPS55161426A JP S55161426 A JPS55161426 A JP S55161426A JP 7090279 A JP7090279 A JP 7090279A JP 7090279 A JP7090279 A JP 7090279A JP S55161426 A JPS55161426 A JP S55161426A
Authority
JP
Japan
Prior art keywords
signal
generated
counter
reset
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7090279A
Other languages
Japanese (ja)
Inventor
Hiromi Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7090279A priority Critical patent/JPS55161426A/en
Publication of JPS55161426A publication Critical patent/JPS55161426A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Abstract

PURPOSE:To continue generating a reset signal repeatedly until a normal operation is restored, by detecting the abnormal operation of a malfunction detection object by the output of a gate element where the output signal of a counter and the pulse signal of the second oscillator are input. CONSTITUTION:The first oscillator 8 and the second oscillator 9 output signals C1 and C2 of an equal frequency, and the generation time of signal C2 is delayed from the generation time of signal C1 by fixed time T. Counter 7 is a binary counter which is reset by signal C1 and counts signal P, and counter 7 generates output signal Q which has the level inverted each time signal p of frequency f is counted by fixed number A. In case that signal C2 is generated while signal Q is ''H'', reset signal R is not generated by gate element 10. In case that signal C2 is generated while signal Q is ''L'', reset signal R is generated.
JP7090279A 1979-06-04 1979-06-04 Malfunction detecting unit Pending JPS55161426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7090279A JPS55161426A (en) 1979-06-04 1979-06-04 Malfunction detecting unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7090279A JPS55161426A (en) 1979-06-04 1979-06-04 Malfunction detecting unit

Publications (1)

Publication Number Publication Date
JPS55161426A true JPS55161426A (en) 1980-12-16

Family

ID=13444917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7090279A Pending JPS55161426A (en) 1979-06-04 1979-06-04 Malfunction detecting unit

Country Status (1)

Country Link
JP (1) JPS55161426A (en)

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