JPS5674662A - Frequency to voltage converter - Google Patents

Frequency to voltage converter

Info

Publication number
JPS5674662A
JPS5674662A JP15202079A JP15202079A JPS5674662A JP S5674662 A JPS5674662 A JP S5674662A JP 15202079 A JP15202079 A JP 15202079A JP 15202079 A JP15202079 A JP 15202079A JP S5674662 A JPS5674662 A JP S5674662A
Authority
JP
Japan
Prior art keywords
becomes
counter
output
circuit
square wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15202079A
Other languages
Japanese (ja)
Inventor
Kunio Miyahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15202079A priority Critical patent/JPS5674662A/en
Publication of JPS5674662A publication Critical patent/JPS5674662A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate erros owing to the pulse intervals of reference clock pulses by forming a circuit which outputs the square waves having the periods coninciding in time mode and having a fixed pulse width for the square wave input data of the frequency to be converted.
CONSTITUTION: When a square wave input 11 becomes 1 from 0, the reset signal 35 of a pulse counter 7 becomes 0 from 1 and the counter 7 assumes an operating state from a reset state. At this instant, the output 33 of an exclusive OR circuit 23 becomes 1 from 0 and a reference frequency generator 21 starts oscillating by means of a square wave input signal 11. The counter 7, inputted with clock pulses 31, starts counting and emits 1 to the counter output 32 at the instant when it counts by preset number. When the output 32 becomes 1, the another input 11 of the circuit 23 is also 1, and therefore the output 33 thereof becomes 0 from 1. At the same time the signal 34 for stopping oscillation function becomes 0 from 1 and the generator 21 stops oscillating.
COPYRIGHT: (C)1981,JPO&Japio
JP15202079A 1979-11-26 1979-11-26 Frequency to voltage converter Pending JPS5674662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15202079A JPS5674662A (en) 1979-11-26 1979-11-26 Frequency to voltage converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15202079A JPS5674662A (en) 1979-11-26 1979-11-26 Frequency to voltage converter

Publications (1)

Publication Number Publication Date
JPS5674662A true JPS5674662A (en) 1981-06-20

Family

ID=15531296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15202079A Pending JPS5674662A (en) 1979-11-26 1979-11-26 Frequency to voltage converter

Country Status (1)

Country Link
JP (1) JPS5674662A (en)

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