JPS54110772A - Pulse duration detector circuit - Google Patents

Pulse duration detector circuit

Info

Publication number
JPS54110772A
JPS54110772A JP1743678A JP1743678A JPS54110772A JP S54110772 A JPS54110772 A JP S54110772A JP 1743678 A JP1743678 A JP 1743678A JP 1743678 A JP1743678 A JP 1743678A JP S54110772 A JPS54110772 A JP S54110772A
Authority
JP
Japan
Prior art keywords
circuit
output
pulse
pulse duration
detector circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1743678A
Other languages
Japanese (ja)
Inventor
Minoru Mahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1743678A priority Critical patent/JPS54110772A/en
Publication of JPS54110772A publication Critical patent/JPS54110772A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To realize a pulse duration detector circuit which can increase the detection accuracy without supplying any high-speed clock pulse from outside by providing a simple pulse generating circuit using a delay circuit to the detector circuit itself.
CONSTITUTION: When input (a) features "1", AND circuit 1 operates since the initial state of output (e) of flip-flop 8 is "0". As a result, flip-flop 2 is set, and output (b) becomes "1" to actuate AND circuit 3. And output (c) is delayed through delay circuit 4 to turn the output of circuit 3 to "0" via NOT circuit 5. This feedback loop functions as a pulse generating circuit until output (b) becomes "0", and output (e) and (b) turn to "1" and "0" respectively when counter 6 counts the pulses up to the fixed number. As a result, pulse input (a) shorter than the pulse duration of output (b), if it exists, can be detected.
COPYRIGHT: (C)1979,JPO&Japio
JP1743678A 1978-02-17 1978-02-17 Pulse duration detector circuit Pending JPS54110772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1743678A JPS54110772A (en) 1978-02-17 1978-02-17 Pulse duration detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1743678A JPS54110772A (en) 1978-02-17 1978-02-17 Pulse duration detector circuit

Publications (1)

Publication Number Publication Date
JPS54110772A true JPS54110772A (en) 1979-08-30

Family

ID=11943965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1743678A Pending JPS54110772A (en) 1978-02-17 1978-02-17 Pulse duration detector circuit

Country Status (1)

Country Link
JP (1) JPS54110772A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594318A (en) * 1982-06-30 1984-01-11 Fujitsu Ltd Pulse width detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594318A (en) * 1982-06-30 1984-01-11 Fujitsu Ltd Pulse width detecting circuit

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