JPS5672553A - Burst error detection circuit - Google Patents

Burst error detection circuit

Info

Publication number
JPS5672553A
JPS5672553A JP14965479A JP14965479A JPS5672553A JP S5672553 A JPS5672553 A JP S5672553A JP 14965479 A JP14965479 A JP 14965479A JP 14965479 A JP14965479 A JP 14965479A JP S5672553 A JPS5672553 A JP S5672553A
Authority
JP
Japan
Prior art keywords
terminal
gate
pulse
burst error
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14965479A
Other languages
Japanese (ja)
Other versions
JPS5837739B2 (en
Inventor
Koichi Otani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14965479A priority Critical patent/JPS5837739B2/en
Publication of JPS5672553A publication Critical patent/JPS5672553A/en
Publication of JPS5837739B2 publication Critical patent/JPS5837739B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end

Abstract

PURPOSE:To detect a burst error continuously at a high speed and also by the real time, by generating a burst error signal by being set by an error pulse, and providing the FF which is reset when the number of continuous nonerror pulses has exceeded the prescribed value. CONSTITUTION:An error pulse which has been detected is provided to the set terminal S of the FF12 from the terminal 11, and the Q terminal is connected to the output terminal 13. As for the AND gate 16, when a output of the FF12 is in a high level, that is to say, a burst error signal is being generated, and also the error pulse is not provided from the AND gate 15, a clock pulse of the terminal 17, that is to say, a nonerror pulse is provided to the clock terminal CK of the counter 14 through the AND gate 16. Also, when the error pulse passes through the NAND gate 15, the counter 14 is reset. When the counter 14 has counted the prescribed value, its output is provided to the OR gate 19, and also it is provided to the reset terminal R of the FF12.
JP14965479A 1979-11-19 1979-11-19 Burst error detection circuit Expired JPS5837739B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14965479A JPS5837739B2 (en) 1979-11-19 1979-11-19 Burst error detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14965479A JPS5837739B2 (en) 1979-11-19 1979-11-19 Burst error detection circuit

Publications (2)

Publication Number Publication Date
JPS5672553A true JPS5672553A (en) 1981-06-16
JPS5837739B2 JPS5837739B2 (en) 1983-08-18

Family

ID=15479937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14965479A Expired JPS5837739B2 (en) 1979-11-19 1979-11-19 Burst error detection circuit

Country Status (1)

Country Link
JP (1) JPS5837739B2 (en)

Also Published As

Publication number Publication date
JPS5837739B2 (en) 1983-08-18

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