JPS5837739B2 - Burst error detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a burst error detection circuit for rapidly and continuously detecting burst error sections in which errors occur intensively in a transmission path in a digital signal transmission system.

Conventionally, this type of burst error detection circuit has not been realized.

A similar circuit to this is one that detects continuous errors as burst errors.If there are N or more (here, M and N are positive integers) error data in a specific M data set, it is detected as a burst error. There were things.

These methods record error pulses that also detect falls on a magnetic tape, read them out, and process them using an electronic computer, making it impossible to continuously detect burst errors at high speed in real time.

It should be noted that conventional detection circuits of this type have been mainly used for detecting errors in fixed transmission lines, and have been used mainly for evaluating transmission quality and for line design.

In mobile communication, burst errors occur relatively frequently due to the unique nature of the communication.

It would be extremely convenient if this burst error state could be detected immediately, the situation at that time could be known, and the error could be dealt with.

The object of the present invention is to provide a burst error detection circuit that can continuously detect burst errors at high speed and in real time and is particularly applicable to fading radio lines.

According to this invention, consecutive non-error pulses are counted by a counter, and an error pulse that occurs after the count exceeds a predetermined value is regarded as the start of a burst error, and after that, the number of consecutive non-error pulses exceeds the predetermined value. If it exceeds the limit, the burst error ends.

For example, as shown in FIG. 1, the detected error pulse is supplied from terminal 11 to set terminal 8 of flip-flop 12.

The Q terminal of flip-flop 12 is connected to output terminal 13.

Continuous non-error pulses are counted and when the count value of the counter 14 exceeds a predetermined value, an output is generated.

For example, the output of the flip-flop 12 is supplied to a NAND gate 15 and an AND gate 16, respectively.
A clock synchronized with the clock at the input terminal 11 is supplied to the gate 16 from the terminal 17 .

The NAND gate 15 is supplied with the error pulse at the input terminal 11, the output of which is supplied to the AND gate 16, through an inverter 18, and further through an OR gate 19 to the reset terminal R of the counter 14.

Therefore, when the output of the flip-flop 12 is at a high level, that is, a burst error signal is occurring, and no error pulse is supplied from the NAND gate 15, the clock pulse at the terminal 17, that is, the non-error pulse is
Clock terminal C of the counter 14 through the ND gate 16
k.

Also, when an error pulse passes through the NAND gate 15, the counter 14 is reset.

When the counter 14 counts a predetermined value, its output is supplied to the OR gate 19 and also to the reset terminal R of the flip-flop 12.

For example, when the error pulse signal shown in FIG. 2A is input from the input terminal 11, the first pulse is input at time t1.
flip-flop 12 is set, and its output is the second
As shown in Figure B, the logic level becomes ``1'' and the terminal 13
outputs a burst error signal.

A counter 14 counts the number of non-error pulses while this burst error signal is being generated.

The counter 14 is reset each time an error pulse signal arrives at the input terminal 11.

The output of the NAND gate 15 is as shown in FIG. 2C, and the output of the OR gate 19 is as shown in FIG. 2E.

Further, the non-error pulse of the AND gate 16 becomes as shown in FIG. 2D.

The count value of the counter 14 is always the number of consecutive non-error pulses.

When this count reaches a preset value, 5 in FIG. 2, an output is generated from the counter 14 at time t2 as shown in FIG.
2 and counter 14 are reset and flip-flop 1
The output of 2 becomes logic "0".

The time width of the burst error detection signal obtained at the output terminal 13 is the sum of the length of the burst error and the time determined by the set value of the counter 14.

FIG. 2G shows the clock at terminal 17.

In order to perform such an operation, it is possible to detect burst errors in which data errors are concentrated and output the length (time from the start to the end of the burst error) by using wiring logic.

Therefore, it can be applied, for example, to high-speed, real-time detection of burst errors in fading radio links.

Note that the burst error signal detected at the output terminal 13 is obtained even when error pulses are not concentrated.

In such a case, since the burst error signal is short, the time width selection circuit 21 may select only the signals having a predetermined time width or more from the output of the terminal 13, if necessary.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an embodiment of a burst error detection circuit according to the present invention, and FIG. 2 is a time chart showing an example of the operation of the circuit shown in FIG. 11... Signal input terminal, 12... Set priority type set reset flip-flop, 13...
...Output terminal, 14...Preset type counter.

Claims (1)

[Claims] 1. A burst error detection circuit comprising a flip-flop that is set by an error pulse to issue a burst error signal, and a counter that counts consecutive non-error pulses and resets the flip-flop when a predetermined value is exceeded.