JPS55151360A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS55151360A
JPS55151360A JP5890579A JP5890579A JPS55151360A JP S55151360 A JPS55151360 A JP S55151360A JP 5890579 A JP5890579 A JP 5890579A JP 5890579 A JP5890579 A JP 5890579A JP S55151360 A JPS55151360 A JP S55151360A
Authority
JP
Japan
Prior art keywords
voltage
operated
signal
buffer
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5890579A
Other languages
Japanese (ja)
Inventor
Akira Miyamoto
Kazuki Yoshitake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5890579A priority Critical patent/JPS55151360A/en
Publication of JPS55151360A publication Critical patent/JPS55151360A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the driving capacity of an integrated circuit by applying a signal from a circuit operated with the first voltage through an inverter operated by the second voltage being larger in absolute value than the first voltage to an output buffer operated by the second voltage. CONSTITUTION:A signal S1 from a circuit 1 operated with low voltage is applied to an inverter 2 operated at high voltage and consisting of a p-type saturable load MOSFETP1 and a p-type active MOSFETP2. When the signal S2 thus shifted in level is applied to the buffer 3 to produce a high output current from the output OUT without increasing the size of the buffer.
JP5890579A 1979-05-14 1979-05-14 Integrated circuit Pending JPS55151360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5890579A JPS55151360A (en) 1979-05-14 1979-05-14 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5890579A JPS55151360A (en) 1979-05-14 1979-05-14 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS55151360A true JPS55151360A (en) 1980-11-25

Family

ID=13097814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5890579A Pending JPS55151360A (en) 1979-05-14 1979-05-14 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS55151360A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326501A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Signal level conversion circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326501A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Signal level conversion circuit

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