JPS55149566A - Facsimile receiver - Google Patents

Facsimile receiver

Info

Publication number
JPS55149566A
JPS55149566A JP5832979A JP5832979A JPS55149566A JP S55149566 A JPS55149566 A JP S55149566A JP 5832979 A JP5832979 A JP 5832979A JP 5832979 A JP5832979 A JP 5832979A JP S55149566 A JPS55149566 A JP S55149566A
Authority
JP
Japan
Prior art keywords
memory
video signal
line
input
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5832979A
Other languages
Japanese (ja)
Inventor
Masao Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JUJO ENG CO Ltd
JUJO ENG KK
Original Assignee
JUJO ENG CO Ltd
JUJO ENG KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JUJO ENG CO Ltd, JUJO ENG KK filed Critical JUJO ENG CO Ltd
Priority to JP5832979A priority Critical patent/JPS55149566A/en
Publication of JPS55149566A publication Critical patent/JPS55149566A/en
Pending legal-status Critical Current

Links

Landscapes

  • Storing Facsimile Image Data (AREA)
  • Facsimile Scanning Arrangements (AREA)

Abstract

PURPOSE: To record the specified white part independently of the presence of control signal, by locating two memories parallelly and inputting them to the memory with the clock selecting the demodulation signal.
CONSTITUTION: In case of the drum type facsimile, when the phase signal interval t2 is made longer as t2', the video signal time is compressed and the white part is extended. To prevent this, the memories 2, 3 are provided, two sets of clocks f1, f2 are prepared, and f1<f2 is taken. Thus, if the control signal is present, the video signal of the first one line is input to the memory 2 at the clock f2, the switch S1 is selected, and the video signal of the next one line is input to the memory 3. While this, the video signal is read out at the clock f1 from the memory 1 and input to the recording circuit 4 and recorded on the receiving paper on the drum 5 at the same time as usual case. When the readout is finished, the switch S2 is selected to the memory 3. That is, during the readout from the memory 2, the video signal of the next one line is input to the memory 3. Accordingly, the circuit 4 records the information one line before the transmitted line.
COPYRIGHT: (C)1980,JPO&Japio
JP5832979A 1979-05-11 1979-05-11 Facsimile receiver Pending JPS55149566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5832979A JPS55149566A (en) 1979-05-11 1979-05-11 Facsimile receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5832979A JPS55149566A (en) 1979-05-11 1979-05-11 Facsimile receiver

Publications (1)

Publication Number Publication Date
JPS55149566A true JPS55149566A (en) 1980-11-20

Family

ID=13081250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5832979A Pending JPS55149566A (en) 1979-05-11 1979-05-11 Facsimile receiver

Country Status (1)

Country Link
JP (1) JPS55149566A (en)

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