JPS55149550A - Superimposing and transmitting system of sub-signal - Google Patents

Superimposing and transmitting system of sub-signal

Info

Publication number
JPS55149550A
JPS55149550A JP5735279A JP5735279A JPS55149550A JP S55149550 A JPS55149550 A JP S55149550A JP 5735279 A JP5735279 A JP 5735279A JP 5735279 A JP5735279 A JP 5735279A JP S55149550 A JPS55149550 A JP S55149550A
Authority
JP
Japan
Prior art keywords
signal
sub
main signal
superimposing
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5735279A
Other languages
Japanese (ja)
Inventor
Sadao Ifukuro
Yasuo Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5735279A priority Critical patent/JPS55149550A/en
Publication of JPS55149550A publication Critical patent/JPS55149550A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/12—Arrangements providing for calling or supervisory signals
    • H04J3/125—One of the channel pulses or the synchronisation pulse is also used for transmitting monitoring or supervisory signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To transmit the sub-signal by superimposing it on the main signal, by inserting the bit of sub-signal between the bits of the main signal, in the transmission system transmitting the main signal with binary RZ code signal. CONSTITUTION:When the sub-signal b in 4-bit constitution is synthesized to the main signal (a), the waveform (c) is obtained and it is transmitted from the transmission section S. That is, the input data Din of main signal of binary RZ code and the clock CLKin are added to the synthesizing section SM, CLKin and the input sub-signal SBin are added to the pattern generating section PTG, and the pattern consisting of 4 bits in response to the sub-signal of an arbitrary number is produced with a fixed interval and is added to the SM to form the superimposing signal. At the reception section R, the signal is amplified and fed to the band pass filter FIL and the timing extraction circuit TIM,and the clock of the waveforms (e), (f) is obtained from the gate G1, and this clock reproduces the main signal and sub-signal.
JP5735279A 1979-05-10 1979-05-10 Superimposing and transmitting system of sub-signal Pending JPS55149550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5735279A JPS55149550A (en) 1979-05-10 1979-05-10 Superimposing and transmitting system of sub-signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5735279A JPS55149550A (en) 1979-05-10 1979-05-10 Superimposing and transmitting system of sub-signal

Publications (1)

Publication Number Publication Date
JPS55149550A true JPS55149550A (en) 1980-11-20

Family

ID=13053176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5735279A Pending JPS55149550A (en) 1979-05-10 1979-05-10 Superimposing and transmitting system of sub-signal

Country Status (1)

Country Link
JP (1) JPS55149550A (en)

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