JPS5514539B2 - - Google Patents
Info
- Publication number
- JPS5514539B2 JPS5514539B2 JP15661676A JP15661676A JPS5514539B2 JP S5514539 B2 JPS5514539 B2 JP S5514539B2 JP 15661676 A JP15661676 A JP 15661676A JP 15661676 A JP15661676 A JP 15661676A JP S5514539 B2 JPS5514539 B2 JP S5514539B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/641—Combinations of only vertical BJTs
- H10D84/643—Combinations of non-inverted vertical BJTs and inverted vertical BJTs
-
- H10P32/1414—
-
- H10P32/171—
-
- H10W10/011—
-
- H10W10/10—
-
- H10W72/00—
Landscapes
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7539963A FR2337432A1 (fr) | 1975-12-29 | 1975-12-29 | Perfectionnement a la structure des circuits integres a transistors bipolaires complementaires et procede d'obtention |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5283080A JPS5283080A (en) | 1977-07-11 |
| JPS5514539B2 true JPS5514539B2 (enExample) | 1980-04-17 |
Family
ID=9164256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15661676A Granted JPS5283080A (en) | 1975-12-29 | 1976-12-27 | Ic and method of producing same |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5283080A (enExample) |
| AU (1) | AU506891B2 (enExample) |
| CH (1) | CH609489A5 (enExample) |
| DE (1) | DE2657822A1 (enExample) |
| FR (1) | FR2337432A1 (enExample) |
| GB (1) | GB1571621A (enExample) |
| NL (1) | NL7614383A (enExample) |
| SE (1) | SE7614560L (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5470781A (en) * | 1977-11-16 | 1979-06-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
| US4338622A (en) * | 1979-06-29 | 1982-07-06 | International Business Machines Corporation | Self-aligned semiconductor circuits and process therefor |
| US4539742A (en) * | 1981-06-22 | 1985-09-10 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3624467A (en) * | 1969-02-17 | 1971-11-30 | Texas Instruments Inc | Monolithic integrated-circuit structure and method of fabrication |
| NL7107040A (enExample) * | 1971-05-22 | 1972-11-24 | ||
| DE2212168C2 (de) * | 1972-03-14 | 1982-10-21 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierte Halbleiteranordnung |
| US3904450A (en) * | 1974-04-26 | 1975-09-09 | Bell Telephone Labor Inc | Method of fabricating injection logic integrated circuits using oxide isolation |
-
1975
- 1975-12-29 FR FR7539963A patent/FR2337432A1/fr active Granted
-
1976
- 1976-12-21 DE DE19762657822 patent/DE2657822A1/de active Granted
- 1976-12-24 AU AU20909/76A patent/AU506891B2/en not_active Expired
- 1976-12-24 GB GB54060/76A patent/GB1571621A/en not_active Expired
- 1976-12-24 NL NL7614383A patent/NL7614383A/xx not_active Application Discontinuation
- 1976-12-27 SE SE7614560A patent/SE7614560L/xx unknown
- 1976-12-27 CH CH1636176A patent/CH609489A5/xx not_active IP Right Cessation
- 1976-12-27 JP JP15661676A patent/JPS5283080A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| SE7614560L (sv) | 1977-06-30 |
| FR2337432A1 (fr) | 1977-07-29 |
| DE2657822C2 (enExample) | 1989-10-05 |
| JPS5283080A (en) | 1977-07-11 |
| AU2090976A (en) | 1978-06-29 |
| AU506891B2 (en) | 1980-01-24 |
| CH609489A5 (en) | 1979-02-28 |
| GB1571621A (en) | 1980-07-16 |
| NL7614383A (nl) | 1977-07-01 |
| DE2657822A1 (de) | 1977-07-07 |
| FR2337432B1 (enExample) | 1979-06-22 |