JPS55142496A - Memory error detection and correction circuit - Google Patents

Memory error detection and correction circuit

Info

Publication number
JPS55142496A
JPS55142496A JP4859079A JP4859079A JPS55142496A JP S55142496 A JPS55142496 A JP S55142496A JP 4859079 A JP4859079 A JP 4859079A JP 4859079 A JP4859079 A JP 4859079A JP S55142496 A JPS55142496 A JP S55142496A
Authority
JP
Japan
Prior art keywords
error
bit
fixed failure
readout
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4859079A
Other languages
Japanese (ja)
Inventor
Katsuhiko Aoki
Noboru Onishi
Eiji Fujiwara
Shigeo Kaneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP4859079A priority Critical patent/JPS55142496A/en
Publication of JPS55142496A publication Critical patent/JPS55142496A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To allow the increase in the number of fixed failure bits at readout data correction, by splitting all the words of memory array into a plurality of word groups, storing the fixed failure bit in every word group on the error registration list, and using it at readout.
CONSTITUTION: In response to the readout data from the memory array 1, the inspection martix 30 indicating the fixed failure location which is split into word group of the inspection circuit 3, produces the syndromes S0WS6 corresponded. Together with them, the data indexed from the matrix indicating the fixed failure bit location in every word group number split into 8 groups in the error registration table 2 with the readout address of the array 1 is fed to the error indication circuit 4 to detect the propriety of the error correction and error bit position. If the syndromes S0WS6 detect the two bit error, they invert the data of bit position indicated by the error information and correct the error of another one bit with the syndrome correction by exclusive logical sum. Thus, the increase in the fixed failure bit number is allowed and the reliability of memory unit is increased.
COPYRIGHT: (C)1980,JPO&Japio
JP4859079A 1979-04-20 1979-04-20 Memory error detection and correction circuit Pending JPS55142496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4859079A JPS55142496A (en) 1979-04-20 1979-04-20 Memory error detection and correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4859079A JPS55142496A (en) 1979-04-20 1979-04-20 Memory error detection and correction circuit

Publications (1)

Publication Number Publication Date
JPS55142496A true JPS55142496A (en) 1980-11-07

Family

ID=12807612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4859079A Pending JPS55142496A (en) 1979-04-20 1979-04-20 Memory error detection and correction circuit

Country Status (1)

Country Link
JP (1) JPS55142496A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010198657A (en) * 2009-02-23 2010-09-09 Oki Semiconductor Co Ltd Memory device
JP2014120195A (en) * 2012-12-12 2014-06-30 Hgst Netherlands B V Method for encoding and decoding with use of combination number system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010198657A (en) * 2009-02-23 2010-09-09 Oki Semiconductor Co Ltd Memory device
JP2014120195A (en) * 2012-12-12 2014-06-30 Hgst Netherlands B V Method for encoding and decoding with use of combination number system

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