JPS55140326A - Fundamental period detecting circuit - Google Patents

Fundamental period detecting circuit

Info

Publication number
JPS55140326A
JPS55140326A JP4823779A JP4823779A JPS55140326A JP S55140326 A JPS55140326 A JP S55140326A JP 4823779 A JP4823779 A JP 4823779A JP 4823779 A JP4823779 A JP 4823779A JP S55140326 A JPS55140326 A JP S55140326A
Authority
JP
Japan
Prior art keywords
signal
cmpa4
input
inverted
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4823779A
Other languages
Japanese (ja)
Inventor
Hiroyuki Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON HAMONDO KK
Original Assignee
NIPPON HAMONDO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON HAMONDO KK filed Critical NIPPON HAMONDO KK
Priority to JP4823779A priority Critical patent/JPS55140326A/en
Publication of JPS55140326A publication Critical patent/JPS55140326A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make it possible to detect the fundamental period of an AC signal in a wide frequency range, by inputting the AC signal to one of a level comparator and by sample-holding positive and negative crest values obtained by phase inversion of the AC signal and inputting them to the other of the level comparator. CONSTITUTION:AC signal Vin 1 is connected to one input terminal of level comparator CMPA4. Meanwhile, signal Vin 1 is inverted by phase inverter INV1, and output signal 2 is input to SH circuit S1 which is constituted by buffers A1 and A2, attenuator A3, switch SW1, and sample hold SH capacitor C1. Output signal 3 of circuit S1 is input as reference voltage Vref to the input end of CMPA4. Output signal 4 of CMPA4 is connected to trigger pulse former T1, and trigger pulse 5 is generated each time signal 4 is inverted, thereby controlling switch SW1. Since the reference voltage value is set to a negative DC voltage value and a positive DC voltage value in section t1 for a positive input signal and section t2 for a negative input signal respectively, the output of CMPA4 is not inverted unless the output of CMPA4 exceeds the reference voltage in the next opposite phase when the level of CMPA4 is inverted, so that malfunctions can be prevented.
JP4823779A 1979-04-18 1979-04-18 Fundamental period detecting circuit Pending JPS55140326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4823779A JPS55140326A (en) 1979-04-18 1979-04-18 Fundamental period detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4823779A JPS55140326A (en) 1979-04-18 1979-04-18 Fundamental period detecting circuit

Publications (1)

Publication Number Publication Date
JPS55140326A true JPS55140326A (en) 1980-11-01

Family

ID=12797827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4823779A Pending JPS55140326A (en) 1979-04-18 1979-04-18 Fundamental period detecting circuit

Country Status (1)

Country Link
JP (1) JPS55140326A (en)

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