JPS55139690A - Semiconductor memory unit - Google Patents

Semiconductor memory unit

Info

Publication number
JPS55139690A
JPS55139690A JP4647379A JP4647379A JPS55139690A JP S55139690 A JPS55139690 A JP S55139690A JP 4647379 A JP4647379 A JP 4647379A JP 4647379 A JP4647379 A JP 4647379A JP S55139690 A JPS55139690 A JP S55139690A
Authority
JP
Japan
Prior art keywords
array
cells
memory cells
wiring
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4647379A
Other languages
Japanese (ja)
Inventor
Toshio Hayashi
Kuniyasu Kawarada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP4647379A priority Critical patent/JPS55139690A/en
Publication of JPS55139690A publication Critical patent/JPS55139690A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To prevent write characteristics from deteriorating near both ends of an array of memory cells by making series resistance components of matrix lines 1 and 2, provided corresponding to memory cells of each word, lower near both ends of the matrix lines than those at the center part. CONSTITUTION:In an array of memory cells consisting of memory cells 5 and matrix lines 1 and 2, lower matrix wiring 2 for several cells near both ends of the array is provided with wiring 7 of low resistance. As a result, when data are written in cells near both the ends of the array, cell current ICELL will not converge on only the cell to be written and the current is decentralized to adjacent cells shorted by wiring 7 of low resistance. As a result, the distribution of cell current SEL is nearly uniform and write characteristics are prevented from deteriorating due to cells near both the ends of the array.
JP4647379A 1979-04-16 1979-04-16 Semiconductor memory unit Pending JPS55139690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4647379A JPS55139690A (en) 1979-04-16 1979-04-16 Semiconductor memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4647379A JPS55139690A (en) 1979-04-16 1979-04-16 Semiconductor memory unit

Publications (1)

Publication Number Publication Date
JPS55139690A true JPS55139690A (en) 1980-10-31

Family

ID=12748152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4647379A Pending JPS55139690A (en) 1979-04-16 1979-04-16 Semiconductor memory unit

Country Status (1)

Country Link
JP (1) JPS55139690A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0380109A2 (en) * 1989-01-27 1990-08-01 Matsushita Electronics Corporation A semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0380109A2 (en) * 1989-01-27 1990-08-01 Matsushita Electronics Corporation A semiconductor memory device

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