JPS55138964A - Facsimile storage converting device - Google Patents
Facsimile storage converting deviceInfo
- Publication number
- JPS55138964A JPS55138964A JP4602179A JP4602179A JPS55138964A JP S55138964 A JPS55138964 A JP S55138964A JP 4602179 A JP4602179 A JP 4602179A JP 4602179 A JP4602179 A JP 4602179A JP S55138964 A JPS55138964 A JP S55138964A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transmitted
- width
- facsimile
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
- H04N1/333—Mode signalling or mode changing; Handshaking therefor
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimiles In General (AREA)
Abstract
PURPOSE:To prevent a transmitted original from stretching in the scanning direction, by making a facsimile signal synthetically by a facsimile signal of the same section as the transmitted original width and a facsimile signal of the additional signal section. CONSTITUTION:A facsimile signal 2 transmitted from the terminal 1 is converted to a binary signal in the digital sampling circuit 6 by the sampling clock generated based upon a synchronizing signal in the signal 2 which has been detected by the detection circuit 4, and is stored in the memory 7. The stored signal is read by the clock which is generated in the transmitted original section read clock generation circuit 9 under control of the synchronizing signal generation circuit 8, and is applied to the synthesis circuit 12. This signal has width 21 of the transmitted original and width of the part 23 of the receiving record picture 22. From the additional signal read clock generation circuit 10 is output a signal to the emaining part of the receiving record picture 22, it is synthesized with a signal from the memory, and is transmitted to the receiving terminal as a signal corresponding to width of the receiving record picture.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54046021A JPS6028177B2 (en) | 1979-04-17 | 1979-04-17 | How to send facsimile signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54046021A JPS6028177B2 (en) | 1979-04-17 | 1979-04-17 | How to send facsimile signals |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55138964A true JPS55138964A (en) | 1980-10-30 |
JPS6028177B2 JPS6028177B2 (en) | 1985-07-03 |
Family
ID=12735387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54046021A Expired JPS6028177B2 (en) | 1979-04-17 | 1979-04-17 | How to send facsimile signals |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6028177B2 (en) |
-
1979
- 1979-04-17 JP JP54046021A patent/JPS6028177B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6028177B2 (en) | 1985-07-03 |
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