JPS5745773A - Facsimile device - Google Patents
Facsimile deviceInfo
- Publication number
- JPS5745773A JPS5745773A JP55119820A JP11982080A JPS5745773A JP S5745773 A JPS5745773 A JP S5745773A JP 55119820 A JP55119820 A JP 55119820A JP 11982080 A JP11982080 A JP 11982080A JP S5745773 A JPS5745773 A JP S5745773A
- Authority
- JP
- Japan
- Prior art keywords
- outputted
- threshold value
- signal
- cpu
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
- H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
- H04N1/413—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
Abstract
PURPOSE:To store a binary data with fidelity to an original at all times to an RAM through serial parallel conversion, by producing a threshold value with a video signal for a prescribed period outputted from a solidstate image sensor. CONSTITUTION:A timing counter 15 counts a clock (a) inputted usually, opens a gate G1 every prescribed value, produces an output c and outputs a corresponding signal d from a line synchronizing flag 18 to a slidstate scanning element 11 and gives interruption to a CPU. The video signal outputted from the element 11 is outputted to a binary circuit 12 according to a shift lock. After this signal binarized at a comparison circuit 122 based on the threshold value from a threshold value generating circuit 121, it is converted into a parallel 8-bit data via a serial parallel conversion register 13 and a tri-state buffer 14, and the video data for one line's share is stored in an RAM5 in parallel every 8-bit according to the read strobe signal g outputted from the CPU.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55119820A JPS5745773A (en) | 1980-09-01 | 1980-09-01 | Facsimile device |
US06/296,034 US4398221A (en) | 1980-09-01 | 1981-08-25 | Facsimile apparatus |
DE3134542A DE3134542C2 (en) | 1980-09-01 | 1981-09-01 | Facsimile machine |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55119820A JPS5745773A (en) | 1980-09-01 | 1980-09-01 | Facsimile device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5745773A true JPS5745773A (en) | 1982-03-15 |
Family
ID=14771050
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55119820A Pending JPS5745773A (en) | 1980-09-01 | 1980-09-01 | Facsimile device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5745773A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02244984A (en) * | 1989-03-17 | 1990-09-28 | Omron Tateisi Electron Co | Ccd picture element interpolating device |
-
1980
- 1980-09-01 JP JP55119820A patent/JPS5745773A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02244984A (en) * | 1989-03-17 | 1990-09-28 | Omron Tateisi Electron Co | Ccd picture element interpolating device |
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