JPS55135454A - Wave detection circuit - Google Patents
Wave detection circuitInfo
- Publication number
- JPS55135454A JPS55135454A JP4273379A JP4273379A JPS55135454A JP S55135454 A JPS55135454 A JP S55135454A JP 4273379 A JP4273379 A JP 4273379A JP 4273379 A JP4273379 A JP 4273379A JP S55135454 A JPS55135454 A JP S55135454A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- counter
- frequency
- pulse
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/06—Demodulator circuits; Receiver circuits
- H04L27/066—Carrier recovery circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Selective Calling Equipment (AREA)
- Mobile Radio Communication Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To obtain the envelope detection output of the burst signal only when the normal burst signal is supplied, by monitoring the burst cycle of the transmission signal with one counter and then monitoring the frequency of the transmission signal with the other counter respectively. CONSTITUTION:The burst signal features the cycle of t2 between t1 and the frequency with frequency f1. With the count number set to n for counter 12, output Q changes from LOW to HIGH at count n to reset DFF11. Counter 13 counts the time between pulses and then supplies the pulse of freqeucny f2 higher than signal frequency f1 via transmission gate 17. At this moment, the clock of the system is appropriate for the pulse of frequency f2. Accordingly, DFF11 is never reset by the output of counter 13 as long as signal f1 features the normal frequency since counter 13 is reset by pulse 2 of signal f1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54042733A JPS5856296B2 (en) | 1979-04-09 | 1979-04-09 | Detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54042733A JPS5856296B2 (en) | 1979-04-09 | 1979-04-09 | Detection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55135454A true JPS55135454A (en) | 1980-10-22 |
JPS5856296B2 JPS5856296B2 (en) | 1983-12-14 |
Family
ID=12644232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54042733A Expired JPS5856296B2 (en) | 1979-04-09 | 1979-04-09 | Detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856296B2 (en) |
-
1979
- 1979-04-09 JP JP54042733A patent/JPS5856296B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5856296B2 (en) | 1983-12-14 |
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