JPS55128963A - Output phase control method for element clock pulse - Google Patents

Output phase control method for element clock pulse

Info

Publication number
JPS55128963A
JPS55128963A JP3508979A JP3508979A JPS55128963A JP S55128963 A JPS55128963 A JP S55128963A JP 3508979 A JP3508979 A JP 3508979A JP 3508979 A JP3508979 A JP 3508979A JP S55128963 A JPS55128963 A JP S55128963A
Authority
JP
Japan
Prior art keywords
signals
control
given
phase
bias amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3508979A
Other languages
Japanese (ja)
Other versions
JPS6313388B2 (en
Inventor
Kenji Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP3508979A priority Critical patent/JPS55128963A/en
Publication of JPS55128963A publication Critical patent/JPS55128963A/en
Publication of JPS6313388B2 publication Critical patent/JPS6313388B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
    • H04N1/36—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device for synchronising or phasing transmitter and receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Scanning Arrangements (AREA)
  • Facsimile Transmission Control (AREA)

Abstract

PURPOSE:To ensure the easy phase control and thus reduce the control time by securing the phase difference of nearly 180 deg. between the 1st the 2nd signals among three reading signals featuring the phase differences and then giving the variable bias amount only to the 1st detection element among three detection elements. CONSTITUTION:In the facsimile device, the mechanical control is given to the relative position relationship among photo sensors 3, 3' and 3'' so that the phase differences 180 deg. and 90 deg. may be secured between signals A and B plus between signals B and C respectively among the 1st-3rd photoelectric reading signals A-C against the element clock plate to which the slit marks are given with the fixed pitch. Then the output of each sensor is amplified through operational amplifiers 61-63 to obtain outputs A'-C' each. The difference between signals A' and B' as well as between B' and C' is detected through operational amplifiers 64 and 65 each, and the output signals D and E are supplied to exclusive OR circuit 67 in order to obtain element clock pulse F featuring double density to the fixed pitch. In this case, the electric bias amount is fixed for amplifiers 62 and 63, and the control is given only to the bias amount of amplifier 61. As a result, the phase control can be facilitated, thus reducing the control time.
JP3508979A 1979-03-27 1979-03-27 Output phase control method for element clock pulse Granted JPS55128963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3508979A JPS55128963A (en) 1979-03-27 1979-03-27 Output phase control method for element clock pulse

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3508979A JPS55128963A (en) 1979-03-27 1979-03-27 Output phase control method for element clock pulse

Publications (2)

Publication Number Publication Date
JPS55128963A true JPS55128963A (en) 1980-10-06
JPS6313388B2 JPS6313388B2 (en) 1988-03-25

Family

ID=12432226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3508979A Granted JPS55128963A (en) 1979-03-27 1979-03-27 Output phase control method for element clock pulse

Country Status (1)

Country Link
JP (1) JPS55128963A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224562U (en) * 1985-07-29 1987-02-14
JPH05160968A (en) * 1992-03-13 1993-06-25 Sony Corp Image reader

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0622071U (en) * 1992-08-27 1994-03-22 株式会社筑水キャニコム Side plate device of carrier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224562U (en) * 1985-07-29 1987-02-14
JPH05160968A (en) * 1992-03-13 1993-06-25 Sony Corp Image reader

Also Published As

Publication number Publication date
JPS6313388B2 (en) 1988-03-25

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