JPS55125662A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS55125662A
JPS55125662A JP3351879A JP3351879A JPS55125662A JP S55125662 A JPS55125662 A JP S55125662A JP 3351879 A JP3351879 A JP 3351879A JP 3351879 A JP3351879 A JP 3351879A JP S55125662 A JPS55125662 A JP S55125662A
Authority
JP
Japan
Prior art keywords
cell
capacitor
memory cell
charge condition
capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3351879A
Other languages
Japanese (ja)
Inventor
Kazuya Kobayashi
Kan Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3351879A priority Critical patent/JPS55125662A/en
Publication of JPS55125662A publication Critical patent/JPS55125662A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the utilization factor of access by providing on a chip a capacitor, the capacity of which is greater than that of a capacitor in a memory cell, to detect the charge condition of the memory cell, and carrying out a refreshing operation in accordance with the charge condition of the memory cell. CONSTITUTION:A memory cell 11 having the same structure as a memory cell 10 is provided on the same chip. The capacity of a capacitor 5 is set to a small level. The cell 11 is refreshed by a sensor amplifier (S/A)8n+1 simultaneously with the cell 10 for matrix. The charge condition after refresh has been carried out is detected 12. When the charge condition is lower than a predetermined level, a refresh demand signal is output. The capacity Cref of a capacitor in the cell 11 is set to Cref<Ccel/m.1/k when the capacity Ccel of the capacitor in the cell 10, the number of line (m) and attenuation constant (k) are greater than one. The refresh cycle is determined by only variations in charge condition of the cell 11 irrespective of the condition of each cell 10 for matrix so that a necessary and sufficient interval can be provided. The interval can be extended several ten times that is a conventional IC. Accordingly, the utilization factor of access can be improved to a great extent.
JP3351879A 1979-03-22 1979-03-22 Semiconductor integrated circuit Pending JPS55125662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3351879A JPS55125662A (en) 1979-03-22 1979-03-22 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3351879A JPS55125662A (en) 1979-03-22 1979-03-22 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS55125662A true JPS55125662A (en) 1980-09-27

Family

ID=12388757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3351879A Pending JPS55125662A (en) 1979-03-22 1979-03-22 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS55125662A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234298A (en) * 1984-05-07 1985-11-20 Hitachi Ltd Semiconductor integrated circuit
JPH01302595A (en) * 1988-05-30 1989-12-06 Nec Ic Microcomput Syst Ltd Semiconductor memory
US4982369A (en) * 1986-11-07 1991-01-01 Fujitsu Limited Self-refresh semiconductor memory device responsive to a refresh request signal
JP2014524098A (en) * 2011-06-30 2014-09-18 シリコン イメージ,インコーポレイテッド Mechanism for facilitating fine-grained self-refresh control of dynamic memory devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234298A (en) * 1984-05-07 1985-11-20 Hitachi Ltd Semiconductor integrated circuit
US4982369A (en) * 1986-11-07 1991-01-01 Fujitsu Limited Self-refresh semiconductor memory device responsive to a refresh request signal
JPH01302595A (en) * 1988-05-30 1989-12-06 Nec Ic Microcomput Syst Ltd Semiconductor memory
JP2014524098A (en) * 2011-06-30 2014-09-18 シリコン イメージ,インコーポレイテッド Mechanism for facilitating fine-grained self-refresh control of dynamic memory devices

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