JPS55124853A - Memory extension system for information processor - Google Patents

Memory extension system for information processor

Info

Publication number
JPS55124853A
JPS55124853A JP3312079A JP3312079A JPS55124853A JP S55124853 A JPS55124853 A JP S55124853A JP 3312079 A JP3312079 A JP 3312079A JP 3312079 A JP3312079 A JP 3312079A JP S55124853 A JPS55124853 A JP S55124853A
Authority
JP
Japan
Prior art keywords
memory
address
jump
instruction
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3312079A
Other languages
Japanese (ja)
Inventor
Shinji Nishikawa
Mitsuru Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3312079A priority Critical patent/JPS55124853A/en
Publication of JPS55124853A publication Critical patent/JPS55124853A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to simply execute the jump to chip address, for an arbitrary memory chip, by tentatively delaying the execution at the replacement of memory chip.
CONSTITUTION: When jump is desired from an arbitrary address in the memory M1 to another arbitrary address in the memory M2, after designating the memory to be jumped with the input and output port output instruction, the jump instruction is executed and the address output A is altered to new address. By delaying the execution of program by the execution time of this jump instruction, memory chip can be selected without any procedure appearently and software development is made easier. When the extended address signal designating the memory M1 is detected to the input and output port P, the latches 51W53 are operated and the instruction cycle can be delayed by the jump instruction time from M1 to M2.
COPYRIGHT: (C)1980,JPO&Japio
JP3312079A 1979-03-20 1979-03-20 Memory extension system for information processor Pending JPS55124853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3312079A JPS55124853A (en) 1979-03-20 1979-03-20 Memory extension system for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3312079A JPS55124853A (en) 1979-03-20 1979-03-20 Memory extension system for information processor

Publications (1)

Publication Number Publication Date
JPS55124853A true JPS55124853A (en) 1980-09-26

Family

ID=12377764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3312079A Pending JPS55124853A (en) 1979-03-20 1979-03-20 Memory extension system for information processor

Country Status (1)

Country Link
JP (1) JPS55124853A (en)

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