JPS55121567A - Computer system for control - Google Patents
Computer system for controlInfo
- Publication number
- JPS55121567A JPS55121567A JP2829279A JP2829279A JPS55121567A JP S55121567 A JPS55121567 A JP S55121567A JP 2829279 A JP2829279 A JP 2829279A JP 2829279 A JP2829279 A JP 2829279A JP S55121567 A JPS55121567 A JP S55121567A
- Authority
- JP
- Japan
- Prior art keywords
- subordinate
- cpu
- host cpu
- address bus
- data bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
Abstract
PURPOSE: To enable a connection between host CPU and subordinate CPU only when subordinate CPU is to transfer data to host CPU, by providing common RAM between host CPU and subordinate CPU and by connecting the address bus and data bus of host CPU and subordinate CPU to common RAM via a switching gate.
CONSTITUTION: Through address bus A-BUSA and data bus D-BUSA of subordinate CPU15A, subordinate CPU-A group 2A connects to ROM16A, RAM17A dedicating itself to subordinate CPU15A, digital input device DI18A which receives fault release signal 20A-R and fault signals 20A-1W20A-10, digital output device DO11A which informs host CPU group 1 that a fault occurs, address bus switching gate 13A and data bus switching gate 14A which send and receive data to and from digital output device DO11A and host CPU group 1, etc. To common RAM12A, the address bus is connected via the above-mentioned gate 13A, and the data bus via the above-mentioned gate 14A.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2829279A JPS6029424B2 (en) | 1979-03-13 | 1979-03-13 | Control computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2829279A JPS6029424B2 (en) | 1979-03-13 | 1979-03-13 | Control computer system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55121567A true JPS55121567A (en) | 1980-09-18 |
JPS6029424B2 JPS6029424B2 (en) | 1985-07-10 |
Family
ID=12244530
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2829279A Expired JPS6029424B2 (en) | 1979-03-13 | 1979-03-13 | Control computer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029424B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6292059A (en) * | 1985-10-18 | 1987-04-27 | Fanuc Ltd | Multiprocessor system |
-
1979
- 1979-03-13 JP JP2829279A patent/JPS6029424B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6292059A (en) * | 1985-10-18 | 1987-04-27 | Fanuc Ltd | Multiprocessor system |
JPH0235343B2 (en) * | 1985-10-18 | 1990-08-09 | Fanuc Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS6029424B2 (en) | 1985-07-10 |
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