JPS55119752A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS55119752A
JPS55119752A JP2706179A JP2706179A JPS55119752A JP S55119752 A JPS55119752 A JP S55119752A JP 2706179 A JP2706179 A JP 2706179A JP 2706179 A JP2706179 A JP 2706179A JP S55119752 A JPS55119752 A JP S55119752A
Authority
JP
Japan
Prior art keywords
circuit
result
parity error
circuits
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2706179A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2706179A priority Critical patent/JPS55119752A/en
Publication of JPS55119752A publication Critical patent/JPS55119752A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To increase the reliability of unit and the operation rate, by comparing the result of input clock count of the main counter circuit and auxiliary counter circuit and displaying failure with the output of the logical product circuit if parity error signal is produced from the both circuits.
CONSTITUTION: The main counter circuit 1 counts the inputs data based on the clock to detect the parity error of the result of the counter with the error detection circuit 3. On the other hand, the auxiliary counter detection circuit 2 had the same constitution as the circuit 1, the input data is counted at the clock, and the parity error of the result of count is detected with the error detection circuit 4. The comparison circuit 7 compares the result of count of the circuits 1 and 2, and if the parity error detection signal is produced from the both of the circuits 3 and 4, the logical product circuit 9 produces the output, and when the output of the circuit 9 is given with coincidence of the result of comparison of the circuit 7, the reliability and operation rate of the unit can be increased by displaying failure.
COPYRIGHT: (C)1980,JPO&Japio
JP2706179A 1979-03-08 1979-03-08 Logic circuit Pending JPS55119752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2706179A JPS55119752A (en) 1979-03-08 1979-03-08 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2706179A JPS55119752A (en) 1979-03-08 1979-03-08 Logic circuit

Publications (1)

Publication Number Publication Date
JPS55119752A true JPS55119752A (en) 1980-09-13

Family

ID=12210546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2706179A Pending JPS55119752A (en) 1979-03-08 1979-03-08 Logic circuit

Country Status (1)

Country Link
JP (1) JPS55119752A (en)

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