JPS55115728A - Level clamp circuit - Google Patents
Level clamp circuitInfo
- Publication number
- JPS55115728A JPS55115728A JP2270179A JP2270179A JPS55115728A JP S55115728 A JPS55115728 A JP S55115728A JP 2270179 A JP2270179 A JP 2270179A JP 2270179 A JP2270179 A JP 2270179A JP S55115728 A JPS55115728 A JP S55115728A
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- potential
- clamp
- high level
- sense circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Read Only Memory (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce the readout time of stored data, by decreasing the time required for the potential change from the high to low level of bit line, by limiting the high level of the bit line. CONSTITUTION:MISFETQc for clamp is provided between the circuit 3 driving the bit line and the sense circuit 2. When the potential on the bit line 1 is greater than the threshold potential VT of FETQc, current starts to flow to FETQc and it is equal to the current in the load element QL when it reaches the clamp voltage Vc and the potential is clamped at the clamp voltage Vc. The clamp of high level of the bit line avoids that the potential on the bit line is too much increased from the required potential to detect high level at the sense circuit 2 and the time when the stored data is outputted to the output terminal via the sense circuit 2 by decreasing the logical amplitude of the bit line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2270179A JPS55115728A (en) | 1979-02-28 | 1979-02-28 | Level clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2270179A JPS55115728A (en) | 1979-02-28 | 1979-02-28 | Level clamp circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55115728A true JPS55115728A (en) | 1980-09-05 |
| JPH02894B2 JPH02894B2 (en) | 1990-01-09 |
Family
ID=12090162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2270179A Granted JPS55115728A (en) | 1979-02-28 | 1979-02-28 | Level clamp circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55115728A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629298U (en) * | 1992-08-29 | 1994-04-15 | 大日化成工業株式会社 | Speaker diaphragm support structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5177153A (en) * | 1974-12-27 | 1976-07-03 | Meiyo Electric | |
| JPS51148348A (en) * | 1975-06-14 | 1976-12-20 | Fujitsu Ltd | Input protection circuit |
| JPS522270A (en) * | 1975-06-24 | 1977-01-08 | Hitachi Ltd | Gate circuit |
-
1979
- 1979-02-28 JP JP2270179A patent/JPS55115728A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5177153A (en) * | 1974-12-27 | 1976-07-03 | Meiyo Electric | |
| JPS51148348A (en) * | 1975-06-14 | 1976-12-20 | Fujitsu Ltd | Input protection circuit |
| JPS522270A (en) * | 1975-06-24 | 1977-01-08 | Hitachi Ltd | Gate circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02894B2 (en) | 1990-01-09 |
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